Abstract: Methods and systems for enhancing the storage and display of video data and other digital content in a set-top box or other television environment so that such data is securely stored and displayed are provided. Example embodiments provide an enhanced display controller (EDC) that executes in an electronic device, such as a set-top box, to provide secure storage and playback of streamed digital content. The EDC creates or identifies a secure storage location and stores the data stream in that secure location in a secure manner, thereby minimizing unauthorized access. In addition, the EDC supports the secure display of the data stream using standard (or proprietary) encryption techniques, and/or obfuscation techniques. The EDC also optionally supports various requirements for complying with the usage limitations typically associated with DRM data content. In one embodiment, the enhanced display controller is a modified set-top display (device) driver that includes a VBI decoder, mechanisms (e.g.

Abstract: A vertical video format converter is disclosed including a memory unit which consists of a plurality of line memories to store input video data in one of the line memories, a filter for multiplying video data items respectively output from line memories by coefficients input into corresponding video data item positions and adding the multiplied data items to output filtered data. In the present invention, the position of the filter center value is not fixed, but can be located arbitrarily and the filter coefficients need not be symmetrical. Moreover, an interpolation may be performed by one-time filtering, resulting in faster data processing.

Abstract: A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines.

Abstract: A video signal processing apparatus which can perform a liquid crystal display without a deterioration of a picture quality even when a CCD sensor of the NTSC system is used at the time of the PAL system is provided. The video signal processing apparatus has a 1H delay circuit and a selecting circuit. Upon PAL system, by switching the selecting circuit once every seven lines and performing a pre-interpolation, the lines are compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system. In case of performing the liquid crystal display, the timing of an interpolation (LCOMP) signal is synchronized with the timing of the EN signal upon PAL system so as to coincide the portion of the lines to be compensated from 485 lines (vertical) of the NTSC system to 575 lines (vertical) of the PAL system with the portion to be thinned out at a rate of 1 line per 7 lines in the liquid crystal display.

Abstract: In a video signal capturing apparatus with a simple construction capable of distinguishing fields in units of a color field, a separation circuit separates from input video signals, vertical synchronizing signals that lead fields in a one-to-one relationship. A field counter formed by, for example, a scale-of-four counter, counts the number of vertical synchronizing signals. Based on the count value of the field counter and values set in a register, a timing generating circuit performs data capture in such a manner that color fields are distinguished from each other. If color field 3 is to be captured, a value “3” is set the register. The timing generation circuit compares a count value from the field counter with the set value “13”. When the count value equals 3, the timing generation circuit starts capture of digital video data in the determined field. An even-odd number determining circuit may be provided for distinguishing (i.e.

Abstract: An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency.

Abstract: In a liquid crystal display (LCD) device, two continuous frame image data to be displayed on a display unit are compared with each other by a comparator circuit, and horizontal and vertical synchronizing signals are regulated in accordance with a comparison result. That is, when the two frame image data coincide with each other, the horizontal and vertical synchronizing signals are not output to the display unit through the controller, in order to decrease the number of scannings of frames to be displayed. Also, when the LCD device has a backlight unit and two frame image data coincide with each other, the backlight unit is turned off.

Abstract: A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.

Abstract: A liquid crystal display control apparatus includes a display on/off data generation circuit for generating plural display on/off data per pixel corresponding to M (M>N, M and N being integers) frame periods of a video output signal in N frame periods of a video input signal on a unit pixel basis in response to gray-scale data of pixel units included in the video input signal, a write control circuit for writing display on/off data per pixel corresponding to M frames of the video output signal generated by the display on/off data generation circuit into a frame memory during N frame periods of the video input signal, and a read control circuit for sequentially reading out, from the frame memory, display on/off data corresponding to M frames of the video output signal written in the frame memory in synchronism with one display scan period of the video output signal, thereby the data written in the frame memory is not gray-scale data but display on/off data of one bit, therefore, a data bus width at a time o

Abstract: To realize image conversion processing by means of filtering using a multi-tap structure without requiring that a memory to use has a high-speed capability, a merge circuit 102 merges sampled input image signals for every plurality pieces of continuous pixel data and outputs signals, and a memory element 103 stores approximately one frame of output data from the merge circuit 102. The memory element 103 outputs signals to a memory element 104 in accordance with outputs from a memory element 107 which stores control data which are calculated in advance. The memory element 104 stores a larger number of input signals received from the memory element 103 than the number of taps of a filtering circuit 106, and outputs signals to a selection circuit 105. The selection circuit 105 selects signals required by the filtering circuit 106 from input signals received from the memory element 104 and outputs signals to the filtering circuit 106.

Abstract: The present invention provides a method and apparatus for providing video output phase control in a decoder. In particular, the present invention provides a decoder that precisely aligns output of video display data with a time stamp associated with the video display data and thereby allows for efficient usage of compressed video buffer memory in the decoder. In one embodiment, the decoder includes a video output processor for displaying video data and a timer connected to the video output processor for providing video output phase control. A method is also provided for providing video output phase control in the decoder.

Abstract: A frame conversion device for switching between a plurality of image signals that are not synchronous and outputting each image signal continuously and synchronously. In addition, a desired signal is extracted from the continuous image signals and then output in parallel with the continuous image signals. The frame conversion device utilizes a frame conversion unit for recording an image signal optionally selected from a plurality of input image signals. A frame unit is utilized for reproducing a recorded signal outputted from the frame conversion unit independent of the operation of the frame conversion unit. The frame conversion unit includes an identification signal assigning part which assigns an identification signal to a non-image region of an image signal selected from a plurality of input signals. Frame-converting storage parts store the selected image signal. A signal output part selectively reads the image signal stored in each frame-converting storage device.

Abstract: A method and device is described herein for displaying a television picture comprised of several standard aspect ratio images on widescreen and standard aspect ratio video monitors. A widescreen image including several smaller aspect ratio images are assembled and broadcast. A receiver with a widescreen monitor display can display the entire widescreen image. A receiver with a conventional aspect ratio monitor display can display a combination of the smaller aspect ratio images. The device includes a frame store for storing image information, image configuration logic for determining a configuration of image information, and frame address logic to write image information to frame store with a configuration according to image configuration logic.

Abstract: A method and apparatus for image processing provides a memory having a plurality of individual parallel buffers constructed from random access memories (RAMs) for storing data related to a group of image pixels. The buffers each store a parallel, identical version of the image data so that an image processor can access data related to a given pixel in the overall data from each buffer simultaneously. An address expander for the buffer rows and buffer columns is used to convert a row and column address of a selected “central” pixel into a plurality of related pixel data addresses offset at predetermined distances from the selected pixel data's address. In this manner, the address expanders enable a group of related pixels, each in a different parallel buffer, to be accessed simultaneously, without requiring the processor to be interconnected with all of the buffers. This substantially reduces the complexity of processor interconnection design, while substantially enhancing processor speed.

Abstract: A video memory system for storing ATSC video image data is configured as three channels, each channel having two banks and each bank including a plurality of memory rows. The exemplary memory system includes a buffer area for holding bit-stream data and six field buffer areas. The field buffer areas are arranged in pairs to form a three frame buffer areas, such that the buffer areas for the two fields in a given frame are allocated in respectively different banks. The video memory system includes an output memory controller which receives macroblocks of decoded image data and divides the received macroblocks into respective upper and lower half-macroblocks, the upper half-macroblock being stored in one field buffer of the frame and the lower half-macroblock being stored in the other field buffer of the frame.

Abstract: A method and apparatus for low-delay conversion of 3:2 pulldown video to progressive format with field averaging is disclosed. The method considers 3:2 pulldown interlaced video that represents a four-frame motion picture film sequence as a ten-field interlaced video field sequence of three, two, three, two video fields per motion picture frame respectively for the four-frame sequence. One step of the method is the step of creating a ten-frame progressive video frame sequence, having a delay of approximately one field time with respect to the ten-field interlaced video sequence. This step is achieved by combining at one field time intervals a top field and a bottom field from the ten-field interlaced video sequence, where, at the time of combination, the top field and the bottom field are the most recently available top and bottom fields corresponding to the same motion picture film frame.

Abstract: An information recording and reproducing apparatus includes a solid-state memory medium for memorizing serial moving-image information and a reproducing circuit for reproducing a plurality of pieces of moving-image information from the solid-state memory medium in parallel.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. The invention decodes HDTV signals using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled phase number control eliminates screen beating artifacts, such as when image includes dither and checker patterns. Programmable parameters, such as tuning value, phase number matrices, and frame offset numbers, may be chosen flexibly to optimize conditions to certain display.

Abstract: A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the ‘extended’ buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.

Abstract: An image display apparatus is provided for reducing occurrences of moving image false-edges by preventing profound changes in “on”/“off” subfield distribution, and for displaying a sharp image that does not appear blurred. This is achieved by effectively dividing one TV field and by displaying a gray level of an input image signal using an “on”/“off” subfield combination, out of possible “on”/“off” subfield combinations for displaying the gray level, in which a number of subfields with large luminance weightings that are “on” is minimized.

Abstract: A system and method of controlling a memory of an HDTV video decoder is disclosed which has a video bit stream write buffer, a bit stream read buffer, a motion compensate buffer, a store buffer and a display buffer and outputs request signals to read/write a data from/into an external memory every time it is needed in order to decode an input video bit stream. The method includes the steps of prioritizing the request signals output and sending an authorization signal in response to each of the request signals.

Abstract: A method and apparatus for changing the number of scan lines in a frame of video data to produce an image represented by the video data that corresponds to a desired aspect ratio. The apparatus includes a pair of finite impulse response filters for processing the decoded chrominance and luminance pixel values stored in memory. The filters permit a plurality of scan lines of chrominance and luminance data to be read and filtered on a continuous basis with any scan line of data being read only once. Thus, the filters provide a very efficient method of providing a frame of a number of output scan lines of chrominance and luminance pixel values that are different from the number of scan lines of chrominance and luminance pixel values in a frame of video data stored in memory.

Abstract: Methods and apparatus for reducing the total amount of memory required to implement a video decoder and to perform a scan conversion operation on decoded video are described. In accordance with the present invention this is accomplished by having an interlaced to progressive (I-P) conversion circuit utilize the same frame memory used to decode the images upon which a conversion operation is performed. In this manner, the images, e.g., frames, which are buffered in the decoder are utilized by both the decoder and I-P conversion circuit thereby eliminating the need for the I-P conversion circuit to be supported with an independent frame memory. Data included in a decoder's frame memories is used to detect moving image areas for purposes of the I-P conversion process. In a specific exemplary embodiment, one of three frames, which is nearest to a present frame, is referred for calculating frame difference signals. Both subsequent and preceding frames are used to detect motion for I-P conversion purposes.

Abstract: A method for replacing parts of a digitally coded picture (11) is proposed. The digitally coded picture (11) may correspond to a sub-picture which is displayed on the screen of a television set (10). In the method, each line of the picture (11) is run length-coded. The replaceable parts of a line of the picture are run length-coded separately. The part which replaces the replaceable, original part of a line of the picture (11) is run length-coded in such a way that it has the same number of data units (data bytes) as the original part of this line of the picture (11). The replacement of the data for the run length coding words is carried out in a memory device (51). The replacement is possible in a simple manner by virtue of the fact that the original part of a line of the picture and the new part of the line of the picture have the same number of data units. Moreover, a device for carrying out the method is also proposed.

Abstract: In a method of generating an enlarged image signal by the use of a field memory, an image signal enlargement processing cycle constituted by n-th to (n+5)-th fields is repeated so that each one field of image signals read in the order of the n-th to (n+5)-th is sequentially processed by a signal processing circuit into video image signals. The signals are supplied by interlaced scanning to a video image reproducer such as an external television or video projector so that an image is displayed on a display screen in the order of an odd-line field and an even-line field. An area to be enlarged is sequentially written into an odd-line block and an even-line block of a field memory and can continuously be moved on the basis of a designation signal from a microcomputer, so that an enlarged image can be scrolled on the display screen.

Abstract: Decoding images encoded on MPEG requires I and P pictures to be held for a long period of time for B picture reproduction, resulting in a greater amount of memory capacity necessary. This image data decoding apparatus has a reverse quantization section, a reverse DCT section, a sequence managing section, a motion compensating section, and a DRAM control section. Reverse quantization and reverse DCT operations are performed on input encoded image data. The sequence managing section determines the type of input pictures and detects sequences where more than one B picture is continuously input. I and P pictures are necessary for the decode operation of B pictures, so they are held in any frame bank. However, a B picture which has already been displayed is unnecessary, so one bank is shared by two B pictures which are continuously input. This results in a smaller number of necessary banks.

Abstract: A multimedia information transfer system includes a multimedia server and a client server system coupled with the multimedia server through a communication network and transfers data transmitted from the multimedia server to a server of the client server system. The multimedia server stores data streams of the multimedia information and reproduces the information. The client requests the multimedia server to transfer data, stores the transferred data block and displays the stored data block concurrently with the storage of the next coming data block.

Abstract: The invention relates to an architecture making it possible to store and transfer still or moving video images, the said architecture comprising at least one input circuit (E1, E2, . . . , En) allowing access for data intended to make up video images, a memory area (M) making it possible to store video images, at least one video image output circuit (S1, S2, . . . , Sj) and a video bus (B) intended to provide for the transfer of information between the memory area (M), the input circuit and the output circuit, characterized in that the memory area (M) is a general-purpose memory and in that the video bus (B) has a width L greater than or equal to the width of the memory area (M).The general-purpose memory is operated in a centralized manner by a control circuit (CTRL).The invention applies to computer platforms dedicated to the transfer of Broadcast quality images or alternatively to video devices for built-up image animation.

Abstract: A video camera comprises a solid state image pickup device, a pulse generator to supply a transfer pulse to read out signals of the solid state image pickup device, A/D converters to convert the signals read out from the solid state image pickup device into the digital signals, and a dynamic RAM which operates in the high speed page mode to store the digital signals. The video camera has a reading circuit in which the time which is required to read out at least one line of the solid state image pickup device is shorter than the maximum permission time to write into the same RAS address in the high speed page mode and the period of the transfer pulse is an integer times as long as the period of the original oscillation clock of the pulse generator.

Abstract: A method for decoding MPEG standard I (Intra-coded) and P (Predictive-coded) picture bit streams using a memory smaller than one video frame of data.

Abstract: A decoding apparatus decodes efficiency coded picture data. The efficiency coded picture data are first decoded per predetermined picture unit, such as slice. The decoded picture data are stored into a memory. Writing and reading to and from the memory are controlled as follows: A writing operation of a first picture unit to the memory starts when a reading operation of a second picture unit from the memory is finished. Here, the second picture unit precedes the first picture unit and display locations of the first and second picture units are identical to each other. The writing operation goes into a waiting mode while the reading operation is being executed.

Abstract: The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.

Abstract: This MPEG Decoder relates to the decoding of an image that can be of a bi-directional type requiring data from two previously decoded images, each image being displayed in two successive fields corresponding to lines with different parities. Each bi-directional image is decoded twice during its display time, a first time as a first field of the image is being directly displayed, and a second time as the second field is being directly displayed.

Abstract: An apparatus for displaying a plurality of compressed images is disclosed, in which a high quality freeze display is made possible with a high vertical resolution and a multiplicity of compressed images can be displayed at the same time on the display screen without increasing the circuit scale extremely. Different video signals are processed for image compression in a plurality of processing circuits, and a synthesized image is supplied to a display unit for displaying four compressed images on the display screen at the same time. In the case of an image sequence display, the image size is compressed into one half in horizontal and vertical directions respectively by the processing circuits, and the odd and even fields are separately written in field memories. Also, in the case of freeze display, all the lines are written alternately in the field memories without compressing them vertically by a filter circuit.

Abstract: A video signal memory holds blocks of data representing luminance and first and second chrominance signals, the first and second chrominance signals being held in interleaved rows within the blocks, data being transferred from said blocks to a temporary store for use by a processor in predicting picture frames from the stored data.

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frames in a compressed format using DCT compression and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder. In operation, any prediction frames needed for motion compensation decompression of the compressed frame are decompressed in the stored DCT decoder module. The compressed frame is decompressed in the decoder module to obtain a decompressed frame.

Abstract: A picture signal record/playback apparatus and method thereof for a time lapse VCR which makes it possible to operate with enhanced stability and greater accuracy in providing picture signals. The apparatus includes a memory unit for storing therein by a per frame unit a plurality of frame picture signals respectively having an inter-frame input time interval, a memory control unit for consecutively reading the picture signals for the plurality of frames from the memory unit so as not to have a time interval therebetween, and a recording unit for recording on a magnetic tape media the plurality of frame picture signals being consecutively read.

Abstract: An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a

Abstract: An electronic video processing system comprises a store (11) for storing data defining plural video clips, and a processor (21, 27, 28, 29) for selecting from the stored video clips a plurality of clips and for selectively combining data defining the selected clips to form data defining a video story. A plurality of representative frames respectively representing selected video edits is displayable to portray a portion of the video story. Also, for each selected clip, a frame representative thereof is displayable together with a pair of smaller frames derived from the first and last frames of the clip.

Abstract: A device for reversing an image of an object includes selector for selecting a reverse mode and control signal generator for generating a plurality of control signals. The control signal generator outputs a down-counting signal when the reverse mode is selected. A memory stores image data when the memory receives a store-enable control signal from the control signal generator and outputs the stored image data when the memory receives an output-enable control signal from the control signal generator. The device also includes an address generator for generating an address at which the image data is stored in the memory according to a control signal received from the control signal generator. During the reverse mode, the address generator generates an address to sequentially access the memory, beginning with a last address of the memory according to the down-counting signal.

Abstract: A multimedia terminal for adapting audio-video signals into a digital data network is provided. The terminal comprises a video decoder, a video encoder, a frame buffer, and a host processor coupled to the frame buffer. The frame buffer has a plurality of memory fields, a system time clock that is switchable from a free running clock to being locked to the analog video signals and a frame buffer logic control circuit which controls the flow of data in and out of the memory fields. The frame buffer is able to operate in two distinct modes.

Abstract: This invention is a method and apparatus for synchronization high quality video like signals. The preferred embodiment is described to synchronize a plurality of mutually unsynchronized video signals as well as passing one or more associated secondary signal with each video signal with a corresponding delay. The selection of one of a plurality of reference signal candidates is shown along with the use of the input signal to provide a fixed delay.

Abstract: An image data decoding and displaying apparatus is equipped with a decode map set for storing decoded data for every frame into an empty areas in a memory. This set contains a plurality of maps each describing a memory area for a frame. A map is changed by a unidirectional counter for every start of a decode operation in frames. A display map set is also provided with a bidirectional counter. Normally, these two counters are incremented every time a frame is decoded and displayed, respectively, so the same maps are referred to from decode operation and display operation. In the display operation, bidirectional counter is decremented by one if data is not decoded in time for display, so that a map for an immediately preceding picture is referred to. In such a case, the previous picture is displayed twice in place of the current picture. Display transition from the current picture to the previous one is performed smoothly changing maps consistently for these pictures.

Abstract: A binarization processing apparatus for converting multi-value image data into binary image data is constructed by pixel groups in which pixels to be binarized are divided into a plurality of groups, a plurality of memories which correspond to the pixel groups and hold data in a binarization processing step, a control unit which performs the reading operation for one of the plurality of memories and simultaneously performs the writing operation for the other memory, and a unit for performing the converting process on the basis of an error diffusing method. The plurality of memories have a single common input/output port.

Abstract: A memory system for processing a digital video signal capable of accessing data in block units includes a detector circuit discriminating whether the memory system is in a reading/writing operation in one of an integer pel mode and a half pel mode. A controller circuit is coupled to the detector circuit and controls access of data in units of m.times.n bit block when the memory system is determined to operate in the integer mode by the detector circuit. The controller circuit controls access of data in units of (m+1).times.(n+1) bit block when the memory system is determined to operate in the half pel mode of a reading operation.

Abstract: A method and apparatus for single-buffered display capture which eliminates a "tearing" problem inherent in certain conventional video display techniques. A video signal including a sequence of frames each having an even field and an odd field is applied to a video capture circuit. First and second sets of lines each representing a different subset of all the lines in a given even or odd field are captured in the video capture circuit and displayed by a video display circuit. The video capture circuit captures the first set of lines in an even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field. The video capture circuit also captures the second set of lines in an odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field.

Abstract: A four-buffer MPEG decoder is provided for decoding MPEG video frames. A four-buffer frame controller and control method manage the four frame buffers including decoding, displaying and discarding of I-frames, P-frames and B-frames so that video data decoding is accelerated. The four-buffer frame controller and control method frees one frame buffer when the frame buffer contains obsolete data, defined as data which is no longer useful for decoding additional frames and for which storage is not necessary for displaying pictures in a correct temporal order. One example of an obsolete frame is a B-frame that is displayed. Another example is a P-frame for I-frame which is no longer used for motion compensation and has been displayed.

Abstract: A video image signal processing and recording system provides for operation in a first mode in which real time display of video is provided and in a second mode in which the video image signals are digitized and stored in a memory and being read out and displayed in response to selection of a display mode for the system. In an enhanced mode operation for the system, increasing of the low light intensity value of the displayed real time images or displayed memory images to compensate for low light conditions or for the effects of back lighting. The video image signal processing and recording system is described with reference to an application in a door entry system for a residential building.