Abstract: An apparatus for picture decoding includes a decoder unit for obtaining decoded picture data by decoding coded data of a video signal coded by at least one of intra-frame coding (I frame), inter-frame coding (P frame), and frame-interpolation coding (B frame); a memory unit including a first frame memory, a second frame memory, and a third frame memory commonly connected to one data bus and one address bus; a display unit for reading the decoded picture data stored in the memory unit in field units based on a display synchronization signal and obtaining interlace-scanned display picture data; and a time control unit for reading the decoded picture data from the first frame memory and the second frame memory as reference frames for the B frame, and for controlling a time difference between a time of writing decoded picture data in the third frame memory, and a time of reading decoded picture data for display by the display unit, from the third frame memory, for reading decoded picture data before rewriting the

Abstract: A decoder for a video signal encoded according to the MPEG-2 standard processes either interlace scan signals or progressive scan signals by dynamically reconfiguring a single high-bandwidth memory. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. This circuitry also detects whether the signal is in interlace or progressive format from the input data stream. When an interlace format signal is being decoded, the memory is partitioned in one configuration and when a progressive format signal is being decoded, the memory is partitioned in another configuration.

Abstract: In this invention, an approach is employed to transmit as a data train in transmitting every frame picture data compressed by using frame correlation and compressed picture data necessary for decoding the corresponding frame in the data train in each of the respective frames and copying compressed picture data of sum sets of compressed picture data included within the respective frames into the respective frames. Thus, in accordance with this invention, in the case where transmission of compressed picture data is carried out in frame units having undergone switching, there is no possibility that degradation of the picture quality has taken place.

Abstract: A picture storage device conveniently employed in conjunction with an electronic still camera or a video camera has an input data converting unit for separating luminance signals of input color picture data having a non-interlaced data format with the sampling rate of the luminance signals and two-route color signals of 4:2:0 into a data string of even-numbered pixels and a data string of odd-numbered pixels, separating the two-route color signals of the color picture data into a data string of the former half pixels and a data string of the latter half pixels, and distributing and re-arraying the separated data, a storage unit having a storage capacity of at least one frame and adapted for storing data in a data re-arraying sequence by the input converting unit, a display data converting unit for converting the data stored in the storage unit into picture-displaying data, and a controller for controlling the input converting unit into synchronization with data writing in the storage unit.

Abstract: In a color image display system formed of a monochromatic CRT or like image display device (102) having a screen (103) for display of images and a rotary filter (106) comprising color filter sections (106R, 106G and 106B) of a plurality of colors; image signals are read from memories (130R, 130G, 130B) at a rate higher than they are written in the memories, so as to reduce flickers. The problem of passing of the reading address over the writing address is solved by reading the image signal of prominent color taking a period in which the passing over occurs. High frequency components of other color image signals are extracted and added to the image signal of each color to thereby enhance the definition of the picture.

Abstract: A structure for supporting a plurality of recording medium drive units includes a base member supporting a floppy disk drive and a DAT drive, an intermediate member supported on the base member and supporting two hard disk drives, and a top member supported on the intermediate member and supporting one or two hard disk drives.The recording medium drive unit support structure is mounted within a housing, within which are also housed a motherboard, a second printed circuit board and a third printed circuit board. The motherboard has mounted thereon a microprocessor for controlling storage of video data on at least one of the hard disks. The second printed circuit board has integrated circuits mounted thereon for receiving plural streams of video information and for selecting for storage fields of video information included in the streams of video information.

Abstract: An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes frame reconstruction or decoder logic which operates to reconstruct a bi-directionally encoded (B) frame with minimal memory requirements. The MPEG decoder operates to decode or reconstruct the frame twice, once during each field display period. The picture reconstruction unit operates to decode or reconstruct the B frame twice, once each during a first field time and a second field time. The first field time substantially corresponds to the time when the first or top field of the picture is displayed, and the second field time substantially corresponds to the time when the second or bottom field of the picture is displayed. This obviates the necessity of storing the reconstructed B frame data, thus reducing memory requirements.

Abstract: In a liquid crystal display (LCD) device, two continuous frame image data to be displayed on a display unit are compared with each other by a comparator circuit, and horizontal and vertical synchronizing signals are regulated in accordance with a comparison result. That is, when the two frame image data coincide with each other, the horizontal and vertical synchronizing signals are not output to the display unit through the controller, in order to decrease the number of scannings of frames to be displayed. Also, when the LCD device has a backlight unit and two frame image data coincide with each other, the backlight unit is turned off.

Abstract: Input image data and audio data divided into a plurality of portions are continuously recorded in a solid-state memory. When the audio data is to be reproduced in units of the portions, a reproducing start address of each portion of the audio data is changed in an order different from that in recording, thereby reproducing the audio data. The image data is divided into a plurality of portions corresponding to the plurality of portions of the audio data. The image data is reproduced in units of the portions. At this time, the reproducing start address of each portion of the image data is changed in an order different from that in recording, thereby reproducing the image data. With this arrangement, even when the image and audio data are reproduced in an order different from that in recording, the reproduced audio data can be confirmed.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: In order to increase a coded data buffer size and provide an OSD area within a 16 Mbit memory for picture signals of NTSC and PAL systems, a display data area of the memory is made 2(N+1)/4N times a frame when a picture size is large.

Abstract: A data collision avoidance circuit is utilized in a memory write control circuit of an image signal processing apparatus for preventing the write and read clocks of a FIFO memory from colliding. The circuit contains a write enable signal generating unit, a window pulse section set up unit, and a write enable signal control unit. The write enable signal generating unit generates a write enable signal in response to the write control odd/even field signal to write the data into the FIFO memory. The window pulse section set up unit generates a window pulse signal having a predetermined pulse width. The time interval of the predetermined pulse width is designed to be greater than a time interval during which write and read clocks of the FIFO memory can potentially collide, and the window pulse signal is generated in response to a read control odd/even field signal.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronisation signal component, the synchronisation signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A random access memory of a digital video decompression processor is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer and a first chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames. A second luminance anchor frame buffer and second chrominance anchor frame buffer are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field.

Abstract: A method for locating a frame position in an MPEG data stream within a computer system is disclosed. MPEG standard is a set of defined algorithms and techniques for the compression and decompression of moving pictures (video) and sound (audio), and the formation of a multiplexed data stream that includes the compressed video and audio data plus any associated ancillary service data. Although the MPEG standard is extremely flexible, there is a fundamental deficiency associated with the packet-oriented nature of the MPEG format, and that is there being no information about the position of each video frame encoded in the data stream. Even though such information can be deduced from the byte-rate, but because the calculation of a frame position depends on a constant byte-rate, a problem may still arise when the byte-rate is non-existent, incorrectly encoded, or constantly changed due to the presence of several packs with varying rates.

Abstract: A field emission device (10) includes a video memory device (12) that receives video data in parallel for each of three colors red, green, and blue. The video memory device (12) provides the video data in color sequential manner to a controller (14). The controller (14) provides appropriate control and data signals in response to the video data to drive a field emission device display (22). The video memory device has a first storage area (30) for a first color (red), a second storage area (32) for a second color (green), and a third storage area for a third color (blue). The second storage area (32) has capacity to store all of the second color of a frame, the first storage area (30) is two-thirds the size of the second storage area (32), and the third storage area (34) is one-third larger than the second storage area (32). The different sizes of the respective storage areas allows for 100% use of memory space without waste.

Abstract: The present invention is a system and method for retrieving segments of stored video programs using closed caption text data. The closed caption text data is extracted from video programming signals received by the invention. Text records based on the extracted closed caption data are generated. Each text record is derived from the closed caption data for a single continuous video segment to which the text record serves as an index or key in retrieving this video segment. Preferably, each text record (a) has sufficient content to adequately describe the content of the video segment to which it serves as an index; and (b) corresponds to a video segment focused on a small number of topics. To accomplish (a) and (b) the present invention generates each text record so that it has a predetermined maximum length and so that it is derived from the closed caption data for a single uninterrupted speaker.

Abstract: A video camera comprises a solid state image pickup device, a pulse generator to supply a transfer pulse to read out signals of the solid state image pickup device, A/D converters to convert the signals read out from the solid state image pickup device into the digital signals, and a dynamic RAM which operates in the high speed page mode to store the digital signals. The video camera has a reading circuit in which the time which is required to read out at least one line of the solid state image pickup device is shorter than the maximum permission time to write into the same RAS address in the high speed page mode and the period of the transfer pulse is integer times as long as the period of the original oscillation clock of the pulse generator.

Abstract: This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

Abstract: Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.

Abstract: In a color image display system formed of a monochromatic CRT or like image display device (102) having a screen (103) for display of images and a rotary filter (106) comprising color filter sections (106R, 106G and 106B) of a plurality of colors; image signals are read from memories (130R, 130G, 130B) at a rate higher than they are written in the memories, so as to reduce flickers. The problem of passing of the reading address over the writing address is solved by reading the image signal of prominent color taking a period in which the passing over occurs. High frequency components of other color image signals are extracted and added to the image signal of each color to thereby enhance the definition of the picture.

Abstract: A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.

Abstract: In a Video processor, an analog composite video signal is converted by an A/D converter (10) to a digital bit sequence in response to a system clock pulse. By using the system clock pulse and horizontal and vertical synchronizing pulses separated from the composite signal, a horizontal blanking interval and a vertical blanking interval are detected by control circuitry (21.about.24) and the read/write operations of a field memory (12) are disabled during the horizontal and vertical blanking intervals and enabled at other times. The picture information from the memory is converted by a D/A converter (13) to analog form in response to the system clock pulse. A multiplex of a digital pedestal level signal and a digital synchronization level signal is supplied to the D/A converter (13) when the memory is disabled.

Abstract: A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value.

Abstract: This invention details a new method of performing frame reordering for decoded digital video picture. By making use of the information on the incoming picture type and the location of the stored bi-directionally predicitive (B) coded, frame in the frame buffer, the frame sequencer can adaptively perform frame reordering for sequence with and without B frame. In addition, the frame reordering is achieved with shorter frame delay and with smaller frame memory.

Abstract: A digital video signal that has been encoded using motion-compensated prediction, transform encoding, and variable-length coding, is decoded using parallel processing. Frames of the video signal are divided into slices made up of a sequence of macroblocks. The signal to be decoded is slice-wise divided for parallel variable-length decoding. Each variable-length-decoded macroblock is divided into its constituent blocks for parallel inverse transform processing. Resulting blocks of difference data are added in parallel to corresponding blocks of reference data. The blocks of reference data corresponding to each macroblock are read out in parallel from reference data memories on the basis of a motion vector associated with the macroblock. Reference data corresponding to each macroblock is distributed for storage among a number of reference data memories.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A television receiver equipped with an internal device produces a deferred source signal in order to alter the amount (X) of deferment in order to allow for a replay or skipping of a portion of a program being viewed. The change in deferment is followed automatically by a resumption of the initial value of deferment. This allows for instant replay or fast forward and subsequent return to the initial condition in an automatic manner.

Abstract: A method is provided for generating a composite video data stream. A first data stream composed of a sequence of frames of video data each having an x-dimension of a preselected number of pixels and a y-dimension of a preselected number of pixels is received. A second data stream composed of a sequence of frames of video data each having a x-dimension of a preselected number of pixels and a y-dimension of a preselected number of pixels is also received. The x- and y-dimensions of the frames of the first data stream are downscaled to produce a sequence of first blocks of pixels. The x- and y-dimensions of the frames of the second data stream are downscaled to produce a sequence of second blocks of pixels. The first blocks are written into a first object buffer associated with a first memory space during first and third ones of four processing phases using a set of counters associated with the first object buffer.

Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.

Abstract: A method is provided for generating a plurality of displays from a composite video data stream comprising a plurality of frames each including two portions, a first portion of each frame containing data defining even fields of respective first and second displays and a second one of the portions of each frame containing data defining odd fields of the first and second displays. During first and second phases of a set of processing phases, data defining the odd and even fields of the first display are extracted from each received frame. Also during the first and third phases, the extracted data defining the odd and even fields of the first display are written into a first object buffer. During second and fourth phases of the set of processing phases, data defining the odd and even fields of the second display are extracted from each received frame. Also during the second and fourth phases, the extracted data defining the odd and even fields of the second display is written into a second object buffer.

Abstract: A method is provided for displaying data received as a composite video data stream, each frame of the composite data stream being composed of a field of data defining a first video display and a subsequent field defining a second video display. The composite video data stream is received and during first and third phases of a set of processing phases, the fields of data defining the first video display are stored in a first object buffer in memory. During second and fourth phases of the set of processing phases, the fields of data defining the second display are stored in a second object buffer in memory. During the first and third phases, the fields of data stored in the first object buffer are retrieved to generate the first display and during the second and fourth phases, the fields of data stoned in the second object buffer are retrieved to generate the second display.

Abstract: An image processing memory integrated circuit used for a signal processing circuit is disclosed. In the bidirectional prediction, pixel values for two-frame images are stored in a memory cell array. The stored pixel values are read on the basis of address of two-dimensional block. The read pixel values of the two images in the block are added by an adder at an appropriate ratio. The resulting inter-image prediction signal and the interpolation signals are outputted to the outside. In the unidirectional prediction, pixel values for one-frame images are stored in a memory cell array. From the memory cell array, pixel values of two-dimensional block expanded from the above-mentioned block are read. The read pixel value is adaptively added to the pixel value delayed by a predetermined number of pixel from the read pixel value through an adder at an appropriate ratio.

Abstract: A memory capable of memorizing a video signal has part of its address area into which an information signal is inhibited from being written. A writing address controller for cyclically specifying writing addresses of the memory cyclically specifies writing addresses in the remaining address area except for the part of address area to allow a plurality of different moving picture scenes to be memorized in the one and same memory.For according to a large capacity main memory, a sub-memory is interposed to access to the main memory with a predetermined information amount being as the unit, thereby facilitating address management of the main memory as well as improving a utilizing effeciency of the main memory.

Abstract: An adapter for use in a multi-media workstation includes a device which accepts real-time video information at a first size, reduces the size to a selected one of a plurality of available sizes and places the reduced real-time video information into a selected area of the video memory of a computer graphic display device. Thereafter, the scaled real-time video information is displayed with other computer graphics applications, in a sub-window of the screen of the display device.

Abstract: A process for synchronizing a scanning circuit of a device for the display of images acquired by a camera having a scanning circuit controlled by a given acquisition clock. The device comprises an input buffer, a processor making it possible to reconstitute each image entering the buffer, a display store in which the images are recorded after processing and a controller able to control the reading or writing of the images in the display store. The process is characterized in that it consists of applying to the scanning circuit an arbitrary clock signal independent of the image synchronization of the signal received. Also, the reading and writing of the display store is controlled in order to obtain repetitions or suppressions of images on display thus absorbing any delay or advance. Further, the processor should have a faster than necessary image compression (average time of one image).

Abstract: The invention relates to a picture memory system for a video printer. Out of continuously incoming video signals, picture signals corresponding to one frame or one field are stored into each of a plurality of semiconductor memories, and the picture just passed can be searched and printed. Therefore, in unilaterally transferred video signals like in television, the desired pictures can be directly printed without incurring the inconvenience of using a video recorder. That is, the multiple steps of recording and reproducing are skipped, and therefore, the degradation of the picture quality can be prevented.

Abstract: The system comprises a memory formed of several disk stores for storing data representing at least one image and a working framestore for temporarily storing one or two frames of image data. Data in the framestore is modified by a processor under operator control. Data is stored in the disk stores by switching selected pixels from each line and selected lines from the or each frame, by way of switches and buffers, to respective disk stores such that the image data is divided into groups which each define a lower resolution version of the whole image frame.

Abstract: According to the picture data coding apparatus of the present invention, the picture data storage unit stores each frame inputted from the pre-process unit, and the frame memory stores the latest-transmitted decoded frame. The frame selection unit judges whether or not a frame under transmission can be displayed. If the frame has been judged to be incapable of being displayed, the frame selection unit judges whether or not each frame stored in the picture data storage unit 103 can be displayed or not, and selects the smallest numbered frame among frames which have been judged to be capable of being displayed. The coding unit predictive codes the selected frame by using the latest-transmitted frame stored in the frame memory 131 as a reference frame, thereby outputting it to the transmission buffer 127. These features can minimize frame skipping even when a frame under transmission becomes incapable of being displayed due to a burst error.

Abstract: A memory address and display control apparatus for an high definition television comprising a memory address controller for controlling memory read/write addresses in response to a motion vector and a control signal, the memory address controller having a display read control circuit, a motion compensation read control circuit, and a raster format write control circuit, a memory unit having a previous frame memory for storing a video signal of a previous frame and a present frame memory for storing a video signal of a present frame, a multiplexing circuit for 2 to 1-multiplexing the output addresses from the memory address controller to alternately address the previous frame memory and the present frame memory in the memory unit, an input/output controller for controlling data input/output of the memory unit in response to frame and invert frame signals, a display controller for receiving video data from the memory unit under the control of the input/output controller and displaying the received video data, a

Abstract: A system for synchronizing asynchronous video signals with a reference signal for input to a digital video processing system has a first-in, first-out (FIFO) buffer for each input signal that writes the digitized video signal into the FIFO under control of an input clock signal derived from the digitized video signal, and reads the digitized video signal from the FIFO under control of the reference signal. An input state machine monitors the digitized video signal at the input and the occupancy of the FIFO to provide a write enable signal to the FIFO so long as the FIFO is not in danger of overflowing. An output state machine monitors the digitized video signal at the output and the occupancy of the FIFO to provide a read enable signal to the FIFO so long as the FIFO is not in danger of underflowing.

Abstract: A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control.

Abstract: Apparatus for storing interlaced video data in a split video memory in noninterlaced form in real video time and without wasted RAM space through the use of a video memory controller that controls transfers between a serial access memory (SAM) including a lower SAM (LSAM) and upper SAM (USAM) and a random access memory (RAM) including a lower RAM (LRAM) and an upper RAM (URAM) of the video memory during free time between video lines when pixel data are not being received, the video memory controller transmitting transfer control signals to the video memory to cause data stored in the LSAM and USAM to be written to the proper page location in the LRAM and URAM after a line has been written in order to save the data before receiving the next line, the controller also generating transfer control signals to cause data in the LRAM and URAM to be read back into the LSAM and the USAM before receiving new data in order to save data that may have already been written into the same page (e.g.

Abstract: A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer.

Abstract: When a plurality of frames of picture data are stored in a divided fashion in a memory for storing one frame of picture data, picture data is stored in each assigned storage area of the storage means. When a plurality of frames of picture data are stored in a divided fashion in a memory, picture data stored in each memory area of the storage is output in the frame mode. Thus, it is possible to effectively avoid the deterioration of the quality of picture data stored in the memory and the output of the picture data of the deteriorated quality that are caused when storing and outputting motion picture data due to reduction of picture data to one half caused by the selection of a field mode with an erroneous operation.

Abstract: The present invention divides a video frame into a series of smaller and smaller quadrants until reaching a single pixel size. By issuing a series of commands, a logical cursor moves within the quadrants to evaluate the frame for changes from the previous frame. Upon detecting a color change, the exact location (identified by a level and a quadrant thereof) is encoded along with a value for the change. As a result of the novel approach disclosed herein, there may be significant storage savings over the prior art.

Abstract: In a method for picture-in-picture insertion, successive frames of a small picture to be inserted into a main picture having successive frames are alternatingly written frame-wise into a memory region of a memory device. A decision signal is generated at a beginning of a display of the main picture, for deciding from which of the two memory regions a stored frame of the small picture is to be read out. Frames of the small picture are read out from whichever memory region enables joint-line-free insertion of the small picture into the main picture.

Abstract: A process is provided for creating a high resolution copy of a target video frame selected from a sequence of video frames, wherein each video frame comprises two interlaced fields.

Abstract: An image processing apparatus for receiving digitized image data, dividing the received image data into a plurality of memory regions in units of a predetermined quantity and storing the same, simultaneously reading the image data stored in the plurality of memory regions by the predetermined quantity and supplying the image data, which have been simultaneously read out, to a vertical digital filter processing.