Abstract: An electronic device includes a chip component, a conductive terminal, a case, and a fixation part. The chip component includes a terminal electrode on an end surface of the chip component. The conductive terminal is connected to the terminal electrode. The case includes an accommodation recess for accommodating the chip component. The fixation part fixes the case to an installation portion.

Abstract: A monolithic ceramic capacitor has a plurality of dielectric layers and a plurality of conductive layers sintered together to form a substantially monolithic ceramic body. The ceramic body defines at least one void between the dielectric and conductive layers. The void is at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer. Within the dielectric body, the first and second conductive layers are connected in a nonconductive manner.

Abstract: An electrical connection contact (5) for a ceramic component (2) is specified. The connection contact (5) comprises a first material (M1) and a second material (M2) arranged thereon, wherein the first material (M1) has a high electrical conductivity and the second material (M2) has a low coefficient of thermal expansion.

Abstract: A multilayer conductor includes at least one separation dielectric layer and a plurality of conductor layers stacked in an alternating manner. Each of the plurality of conductor layers includes a first conductor sublayer and a second conductor sublayer separated from the first conductor sublayer by a sublayer dielectric layer. The second conductor sublayer at least partially overlaps with the first conductor sublayer in each of the plurality of conductor layers. The multilayer conductor is included, for example, in a device including a magnetic core adjacent to at least part of the multilayer conductor.

Abstract: A ceramic electronic component with metal terminals comprising a chip component of approximately parallelepiped shape having a pair of terminal electrodes, and a pair of metal terminal parts provided in accordance with the terminal electrodes. The terminal electrode is formed by wrapping around a part of side faces from an end face of the chip component. The metal terminal part comprises a connecting part connecting to the terminal electrode and including a connecting face extending approximately parallel to the end face, plurality of joint parts connecting to the connecting part and including a joint face extending in a different direction of the connecting face, and plurality of mounting parts connecting to the joint parts and including a mounting part upper face extending approximately parallel to any one of the side faces which is different direction of the joint face by taking predetermined spaces.

Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.

Abstract: The capacitor includes at least: a capacitor body; two lead wires provided on one end surface; a projecting portion provided at a substantially central portion of another end surface; and at least two relief valves provided on the another end surface. On the another end surface, the at least two relief valves are arranged in substantially rotational symmetry with respect to the projecting portion. Further, an axial center line of the projecting portion and an axial center line of the capacitor substantially correspond to each other. Also provided are a capacitor case to be used the capacitor and a substrate provided with a circuit using the capacitor.

Abstract: An electrical connector includes a housing, a pair of terminals and two first conductive traces. The housing comprises two fixing grooves that support the terminals. Each terminal comprises a base, an extending piece extending from the base and a resilient arm extending from the base. The extending piece comprises a first contact portion and the resilient arm comprises a second contact portion for electrically connecting an electronic device. The two first conductive traces are connected to the pair of terminals, an end portion of the each first conductive trace is electrically connected to the first contact portion of the corresponding terminal, and the other end portion of the each first conductive trace is configured to electrically connect to a circuit board.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body including dielectric layers; and first and second inner electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic body, the first and second inner electrodes being alternately laminated with a difference in printing widths therebetween, wherein a difference ratio between the printing widths of the first and second inner electrodes is 20 to 80%. According to embodiments of the present invention, a multilayer ceramic electronic component having excellent reliability and withstand voltage characteristics may be realized, by reducing the occurrence of cracking through a reduction in the influence of step height while securing high capacitance.

Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.

Abstract: There is provided a multilayered ceramic electronic component having a reduced thickness and exhibiting hermetic sealing. In multilayered ceramic electronic component, an external electrode includes two layers, that is, first and second layers, and the first and second layers contain glass with different compositions, respectively. Therefore, the multilayered ceramic electronic component having high reliability, such as strong adhesion between the external electrode and the internal electrode, prevention of glass exudation, or the like, may be obtained.

Abstract: A laminated electronic component includes outer terminal electrodes including lower plating films including metal particles having an average size of 0.5 ?m or less, the lower plating films being formed by directly plating an outer surface of an electronic component body such that the lower plating films are electrically connected to exposed portions of inner conductors. The outer terminal electrodes may further include upper plating films formed on the lower plating films, the upper plating films being defined by one or more layers. Metal particles defining the upper plating films may have an average size of 0.5 ?m or less. The metal particles defining the lower plating films may be Cu particles.

Abstract: The present invention relates to a capacitor arrangement having a capacitor and a first terminal plate and a second terminal plate. The capacitor has a first contact face and a second contact face arranged opposite one another. The terminal plates are each connected to one of the contact faces and have protrusions on one end suitable for engaging in recesses in a power rail.

Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.

Abstract: A ceramic electronic component includes a ceramic element assembly and external electrodes. The external electrodes are disposed on the ceramic element assembly. The external electrodes include an underlying electrode layer and a first Cu plating film. The underlying electrode layer is disposed on the ceramic element assembly. The first Cu plating film is disposed on the underlying electrode layer. The underlying electrode layer includes a metal that is diffusible in Cu and a ceramic bonding material. The metal that is diffusible in Cu is diffused in at least a surface layer in the underlying electrode layer side of the first Cu plating film.

Abstract: A capacitor includes a capacitor body made of a dielectric, a first internal electrode, a second internal electrode, a first signal terminal, a second signal terminal, and a grounding terminal. The first and second signal terminals are connected to the first internal electrode. The grounding terminal is disposed on the outer surface of the capacitor body so as to be connected to the second internal electrode. The grounding terminal is connected to the ground potential. The grounding terminal includes a plating layer which is disposed on the capacitor body and which is connected to the second internal electrode.

Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.

Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.

Abstract: [Problem to be Solved] To provide a helical capacitor for controlling a high-frequency power which flows in power lines, and a manufacturing method of the helical capacitor. [Solution] A helical capacitor is constituted by helically spiraling a belt shape capacitor line 1001 which includes an internal metal body to be a helically spiraled belt-shape internal electrical conductor, a dielectric film covering the internal electrical conductor, and an electrically conductive layer covering the dielectric film. The capacitor line of belt shape 1001 can be wrapped around the internal support body 1200. Internal metal body lead terminals 1311, 1321 are respectively formed at both ends of the internal metal body, and electrically conductive layer lead terminals 1312, 1322 can be respectively formed at both ends of the electrically conductive layer.

Abstract: A highly reliable electronic device that prevents entry of a plating solution via an external electrode and entry of moisture of external environment inside thereof, and generates no soldering defects or solder popping defects which are caused by precipitation of a glass component on a surface of the external electrode. The electrode structure of the electronic device is formed of Cu-baked electrode layers primarily composed of Cu, Cu plating layers formed on the Cu-baked electrode layers and which are processed by a recrystallization treatment, and upper-side plating layers formed on the Cu plating layers. After the Cu plating layers are formed, a heat treatment is performed at a temperature in the range of a temperature at which the Cu plating layers are recrystallized to a temperature at which glass contained in a conductive paste is not softened, so that the Cu plating layers are recrystallized.

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract: The two channel audio surround sound circuit with automatic level control includes a right amplifier, a left amplifier, a right automatic level control and a left automatic level control. A right input is coupled to a positive input of the left amplifier through the right automatic gain control. The right input is coupled to a negative input of the right amplifier and coupled to the output of the right amplifier with one resistor. A left input is coupled to a positive input of the right amplifier through the left automatic gain control. The left input is coupled to a negative input of the left amplifier and coupled to the output of the left amplifier with another resistor.

Abstract: A first internal conductor has a first portion. A second internal conductor has a lead portion and a main electrode portion. The second internal conductor is arranged in the same layer as the first internal conductor. A third internal conductor has a lead portion and a main electrode portion. The third internal conductor is arranged so as to be adjacent to the second internal conductor in a laminate direction. A fourth internal conductor has a lead portion and a main electrode portion. The fourth internal conductor is arranged so as to be adjacent to the third internal conductor in the laminate direction. When the laminate body is viewed from the laminate direction, the main electrode portion of the third internal conductor overlaps with the main electrode portions of the second and fourth internal conductors.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract: A surface mount type electronic component has a dielectric element body, electrodes, lead conductors, and lead wires. The dielectric element body has principal faces and side faces. One electrode is formed on one principal face, the other electrode is formed on the other principal face, and the electrodes face each other. A first portion of one lead conductor is laid on one side face. A first portion of the other lead conductor is laid on another side face. First portions of the lead wires are connected to the corresponding first portions of the lead conductors.

Abstract: An electronic component is provided which includes external electrodes having a multilayer structure of first and second sintered electrode layers that are densely sintered and have less possibility of causing poor appearance and decreased reliability in electrical connection. The external electrodes include a first sintered electrode layer and a second sintered electrode layer containing different metals. The first and second sintered electrode layers contain a borosilicate glass containing an alkali metal.

Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.

Abstract: In a ceramic electronic component, an electrically conductive resin layer is arranged to cover a thick film layer and to extend beyond the end of the thick film layer by at least about 100 ?m and a plating layer is arranged to cover the electrically conductive resin layer except a region having a dimension of at least about 50 ?m and extending along the end of the electrically conductive resin layer. Consequently, the concentration of the stress is reduced.

Abstract: An electronic component is provided which includes external electrodes having a multilayer structure of first and second sintered electrode layers that are densely sintered and have less possibility of causing poor appearance and decreased reliability in electrical connection. Each external electrode includes a first sintered electrode layer and a second sintered electrode layer. The first sintered electrode layer contains a first borosilicate glass containing an alkali metal in which there is 85% to 95% by weight of silicon and 0.5% to 1.5% by weight of the alkali metal based on 100% by weight of all contained elements other than boron. The second sintered electrode layer contains a second borosilicate glass containing an alkali metal in which there is 65% to 80% by weight of silicon and 3.5% to 8.0% by weight of the alkali metal based on 100% by weight of all contained elements other than boron.

Abstract: A chip-type electronic component includes a ceramic chip body, an external electrode formed on the chip body, a conductive elastic resin film made of a mixture of metal powder and elastic resin and formed to cover the external electrode, and a metal plating film. The metal powder is exposed at an obverse surface of the conductive elastic resin film. The metal plating film is formed on the obverse surface of the conductive elastic resin film at which the metal powder is exposed.

Abstract: An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board.

Abstract: A multilayer ceramic electronic component includes a skittered laminated body including internal electrodes that have a strength that is greater than that of ceramic layers provided therein. End portions of the internal electrodes protrude from end surfaces of the laminated body and are deformed so as to extend along the end surfaces by a barrel polishing process using balls. When external electrodes are formed on the end surfaces of the laminated body, a large contact area with the internal electrodes can be obtained. Therefore, a reliability of the electrical connection between the electrodes is definitely secured.

Abstract: A method of fabricating high resistivity thin film resistors. An isolation region is formed on a substrate to isolate the active regions. A polysilicon layer is formed above the substrate. A diffusion barrier layer is formed above the polysilicon layer. Lightly doped ions are implanted in the polysilicon layer. The substrate is annealed at a high temperature. The diffusion barrier layer and the polysilicon layer are patterned to form a high-resistive thin film resistor. Spacers are formed on the sidewalls of the high-resistive thin film resistor.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and/or bottom surfaces of the device.

Abstract: A multilayer capacitor includes: a dielectric element; a pair of first internal conductors with same polarity disposed in the dielectric element to be adjacent to each other while being separated from each other by the dielectric layer; first leadout portions led out from the pair of first internal conductors respectively, one being provided for each of the first internal conductors; a pair of second internal conductors with same polarity disposed in the dielectric element to be adjacent to each other while being separated from each other by the dielectric layer; and second leadout portions led out from the pair of second internal conductors respectively, one being provided for each of the second internal conductors, wherein the first leadout portion and the second leadout portion led out respectively from the first internal conductor and the second internal conductor disposed adjacent to each other are led out to substantially the same positions in side faces facing each other of the dielectric element, resp

Abstract: A C-shaped combination capacitor assembly has a C-shaped shell, multiple capacitors, two conducting wires, two lead wires and encapsulant. The capacitors are mounted in the C-shaped shell. The conducting wires connect the capacitors in parallel. The two lead wires connect respectively to the conducting wires and protrude from the C-shaped shell. The encapsulant fills the C-shaped shell and covers and seals the capacitors, the conducting wires and the lead wires inside the C-shaped shell.

Abstract: A chip capacitor that includes a first and second terminal and a plurality of first and second conductive plates. The first terminal has a first interfacial attachment area that is adapted to be attached to a host substrate. The second terminal has a second interfacial attachment area also adapted to be attached to a host substrate. The first interfacial attachment area and the second interfacial attachment area separated by at least one relatively thin isolation strip such that the first and second interfacial attachment areas generally approach covering the entire attaching area of the chip capacitor. The plurality of first conductive plates are coupled to the first terminal and the plurality of second plates are coupled to the second terminal. In one embodiment, approximately 50% of the periphery of each first and second conductive plate is coupled to the respective first and second terminals.

Abstract: Terminal electrodes 11 and 12 of a main body 2 of a multilayer capacitor 1 are connected to electrode connection parts 21A and 22A of a pair of external terminals 21 and 22 formed by a metal material. At the bottom part of the electrode connection part 21A, an external connection part 21B connected to the electrode connection part 21A is formed. At the bottom part of the electrode connection part 22A, an external connection part 22B connected to the electrode connection part 22A is formed. The widths of the terminal electrodes 11 and 12 and the widths of the external connection parts 21B and 22B are substantially the same, but the widths of the electrode connection parts 21A and 22A are formed narrower. Due to this, propagation of vibration can be suppressed and generation of noise reduced.

Abstract: A method and apparatus is provided that pertains to a low inductance capacitor. The capacitor has a first surface electrically interconnected to a plurality of conductive electrodes and one or more second surfaces electrically interconnected to a plurality of electrodes interposed between the electrodes electrically interconnected to the first conductive surface. A dielectric layer separates the layered plurality of electrodes. The one or more second conductive surfaces are positioned within the body of the layered electrodes, such that the distance between the terminations of the first conductive surface and the one or more second conductive surfaces is shortened to lower inductance.

Abstract: Larger ceramic chip capacitors are reliably mounted with minimal risk of flexure induced cracking on circuit boards by adding terminal extensions to one face of the capacitor and soldering across all or part of the extensions. A ball grid array is preferred.

Abstract: A multilayer capacitor having a dielectric body formed by stacking dielectric sheets. At the outside of the dielectric body are arranged a pair of a first terminal electrode and a second terminal electrode insulated from each other and is arranged at least one first linkage electrode insulated from the first terminal electrode and the second terminal electrode. A first internal electrode is stacked inside the dielectric body via dielectric sheets and is connected to the first terminal electrode. A second internal electrode to be connected to the second terminal electrode is further stacked inside the dielectric body via dielectric sheets. A first polarity conductor to be connected to the first internal electrode through an external first linkage electrode is further stacked inside the dielectric body via dielectric sheets.

Abstract: Surface mount capacitors are made having ultra-small dimensions of length, width and height. For example, capacitors of 0402 size and smaller may be produced having lower height than has been achieved in the prior art. The components have L-shaped terminations on respective ends thereof, providing bottom lands for mounting to a circuit board. At most, the component will have top lands of negligible size to provide a large gap width between the terminations across the top surface of the component. In some embodiments, the top surface may also include orientation indicia located thereon. The invention also provides improved methodology for terminating a capacitor or other surface mount component.

Abstract: A multilayer electronic device comprised of a capacitor body in which a plurality of internal electrodes are separately arranged in a plurality of blocks via ceramic layers. At least one lead is led out from each internal electrode. The terminal electrodes connected to each lead is arranged at the side faces of the capacitor body. The polarities of the voltages supplied to the nearby terminal electrodes in the same side face differ.

Abstract: A low-voltage, low-inductance device for storing electrical charge in a snubber circuit and a method of minimizing inductance in the snubber circuit using the device, wherein the device includes a plurality of extended electrodes, in parallel or series, that are joined to a positive conductor terminal at one end spray and at a negative conductor terminal at the other end spray so that end sprays of adjacent extended electrodes are alternately joined to the positive and negative conductor terminals. Accordingly, current flowing though adjacent extended electrodes is of substantially equal intensity but different in direction. As a result, inductance produced effectively cancels out that of adjacent extended electrodes.

Abstract: The invention provides a multilayer ceramic capacitor capable of preventing the occurrence of cracks by inhibiting the multilayer capacitor from expanding in a stacking direction and a width direction. The multilayer ceramic capacitor includes a capacitor element (10) in which dielectric layers (11a and 11b) and internal electrodes (12) are alternately stacked. The capacitor element (10) is obtained by stacking and firing a dielectric paste layer and an internal electrode paste layer. An expansion coefficient x in the stacking direction lies between −0.05i% and 0.05i% inclusive, where i denotes the number of dielectric layers (11a), preferably the expansion coefficient x is 0% or less, or more preferably the expansion coefficient x lies between −10% and 0% inclusive. Preferably, an expansion coefficient y in the width direction lies between −0.05i% and 0% inclusive.

Abstract: A bypass circuit includes a planar electrode layer which is mounted between a pair of dielectric layers. The electrode layer generally is centered inwardly with respect to the dielectric layers leaving an outward margin of dielectric material. One of the dielectric layers has two spaced apart contact members, each having a different polarity from the other. A resistive layer is centered on the other dielectric layer. The contact members extend onto end portions of the dielectric layers and electrically connect to opposite ends of the resistive layer. The electrode layer is isolated from electrical contact with any conductor and is buried within the dielectric layers. The electrode layer, in combination with the dielectric layer on which the contact members are mounted and the contact members, allow development of a selected value of capacitance between the contact members.

Abstract: Embedded green multi-layer ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates are provided. A first set of electrodes is printed on a ceramic tape. A first dielectric layer is placed over the first set of electrodes and the ceramic tape. A second set of electrodes is printed on the first dielectric layer. A second dielectric layer is placed over the second set of electrodes and the first dielectric layer. A third set of electrodes is printed on the second dielectric layer. The sheet is then cut to form separate green multi-layer ceramic capacitor chips. The green multi-layer ceramic capacitor chips are then placed in a cavity formed by ceramic tape.

Abstract: The multilayer electronic device comprises a dielectric body formed by stacking dielectric layers. Flat first internal electrodes and flat second internal electrodes insulated via dielectric layers and arranged facing to the first internal electrodes are alternately stacked. First through-hole electrodes are connected to the first internal electrodes by penetrating, penetrate the second internal electrodes without connecting thereto and extend crossing the internal electrodes. The second through-hole electrodes are connected to the second internal electrodes by penetrating, penetrate the first internal electrodes without connecting thereto and extend crossing the internal electrodes. The first terminal electrodes are arranged on the outer surface of the dielectric body and connected to the first through-hole electrodes.

Abstract: A multilayer electronic device comprised of a capacitor body in which a plurality of internal electrodes are separately arranged in a plurality of blocks via ceramic layers. At least one lead is led out from each internal electrode. The terminal electrodes connected to each lead is arranged at the side faces of the capacitor body. The polarities of the voltages supplied to the nearby terminal electrodes in the same side face differ.