Abstract: A multilayer ceramic capacitor includes a ceramic body; first and second internal electrodes including first and second body parts overlapped with each other and first and second lead-out parts having an overlap region and exposed to one surface of the ceramic body; first and second external electrodes formed on one surface of the ceramic body; and an insulating layer formed on one surface of the ceramic body, wherein first and second connection surfaces extended from end portions of the first and second body parts to end portions of the first and second lead-out parts are inclined, and when half of length of the internal electrode is defined as A and length from a center of the ceramic body to a starting point of the connection surface is defined as B, B/A satisfies 0.03?B/A?0.90.

Abstract: There is provided a multilayered ceramic capacitor, including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer formed below the active layer, the lower cover layer being thicker than the upper cover layer; first and second external electrodes; at least one pair of first and second internal electrodes repeatedly formed inside the lower cover layer, wherein, when A is defined as 1/2 of an overall thickness of the ceramic body, B is defined as a thickness of the lower cover layer, C is defined as 1/2 of an overall thickness of the active layer, and D is defined as a thickness of the upper cover layer, a ratio of deviation between a center of the active layer and a center of the ceramic body, (B+C)/A, satisfies 1.063?(B+C)/A?1.745.

Abstract: A direction change of space formed in an etching target layer can be suppressed while maintaining an etching selectivity for the etching target layer against a mask. A semiconductor device manufacturing method MT includes exciting a first gas by supplying the first gas containing a fluorocarbon gas, a fluorohydrocarbon gas and an oxygen gas into a processing chamber 12 (ST2); and exciting a second gas by supplying the second gas containing an oxygen gas and a rare gas into the processing chamber (ST3), and a cycle including the exciting of the first gas (ST2) and the exciting of the second gas (ST3) is repeated multiple times.

Abstract: A multilayer body includes an inner layer portion, and a first outer layer portion and a second outer layer portion with the inner layer portion therebetween. The inner layer portion includes a conductive layer arranged closest to a first principle surface side to a conductive layer arranged closest to a second principle surface side in a stacking direction. The first outer layer portion includes a first dielectric layer arranged closest to the first principle surface side. The second outer layer portion includes an outer portion including a second dielectric layer arranged closest to the second principle surface side and an inner portion including a first dielectric layer arranged next to the outer portion at the first principle surface side.

Abstract: A multilayer ceramic capacitor includes a ceramic main body including an inner layer portion including third ceramic layers and a plurality of inner electrodes arranged at interfaces between the third ceramic layers, and first and second outer layer portions respectively including first and second ceramic layers, the first and second ceramic layers being arranged vertically so as to sandwich the inner layer portion. The third ceramic layers and the first and second outer layer portions contain a perovskite-type compound represented by ABO3 where A contains one or more of Ba, Sr, and Ca, B contains one or more of Ti, Zr, and Hf, and O represents oxygen) as a main component. Where a rare-earth element concentration (CR) in the third ceramic layers is compared to a rare-earth element concentration (Cr) in outermost layer portions including at least outermost surfaces of the first and second outer layer portions, CR>Cr (inclusive of Cr=0).

Abstract: There is provided a multilayer ceramic electronic component including a lamination main body including a plurality of inner electrodes. When T1 represents a distance between vertically adjacent inner electrodes in a central portion of the lamination main body, and T2 represents a distance between vertically adjacent inner electrodes at an edges of the inner electrodes in a widthwise direction, a ratio (T2/T1) of T2 to T1 is 0.80 to 0.95.

Abstract: There is provided a multilayer ceramic electronic component, including: a multilayer body having a dielectric layer; and a plurality of internal electrode layers provided in the multilayer body, and having ends exposed to at least one face of the multilayer body, wherein, a ratio of T2 to T1 (T2/T1) ranges from 0.70 to 0.95, when T1 represents a thickness of a capacity formation portion formed by overlapping the plurality of internal electrode layers and T2 represents a distance between ends of outermost internal electrodes arranged on one face of the multilayer body to which the ends of the internal electrodes are exposed, and a thickness D1 of the multilayer body, in which the capacity formation portion is formed, is greater than a thickness D2 of a first side of the multilayer body to which the ends of the internal electrodes are exposed.

Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.

Abstract: There is provided a multilayered ceramic electronic component including: a ceramic body in which a plurality of dielectric layers are stacked; a plurality of first and second internal electrodes formed on at least one of the dielectric layers and alternately exposed through both ends of the ceramic body in a stacking direction of the ceramic body; an a step compensation cover including a ceramic material having a viscosity higher than that of a ceramic material included in the ceramic body and formed on at least one of an upper surface and a lower surface of the ceramic body.

Abstract: A laminated ceramic capacitor includes multiple dielectric layers, internal electrodes having Cu as the primary component and embedded between the dielectric layers, and external electrodes. The dielectric layers contain a primary component comprised of a CaZrO3 compound and auxiliary components that include Mn, B, Si, and Li wherein a primary phase comprised of the primary component, segregation phases containing Ca and at least one of the auxiliary components, and secondary phases containing at last Ca and Zr are formed. The ratio of Ca to Zr in the secondary phases is smaller than the ratio of Ca to Zr in the primary phase, and the number of secondary phases with a diameter of 100 nm or greater in a cross section of the dielectric layers averages 30 or less per 10 square ?m.

Abstract: A monolithic electronic component includes a laminate including a plurality of stacked insulating layers and a plurality of internal electrodes which extend between the insulating layers and which have end portions exposed at predetermined surfaces of the laminate, first plating layers disposed on the predetermined surfaces of the laminate, and second plating layers disposed on the first plating layer. The first plating layers are made of a metal different from that used to make the internal electrodes. The first plating layers are formed by electroless plating. The second plating layers are formed by electroplating.

Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition are disclosed. The method generally includes the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. The methods provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.

Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.

Abstract: A multilayer ceramic capacitor includes a ceramic multilayer body including dielectric layers and inner electrodes stacked on top of one another with the dielectric layers interposed between a corresponding pair of the inner electrodes. The dielectric layers each include a perovskite-type compound including Ba and Ti. A boundary layer including Mg and Mn is located at an interface between an outermost inner electrode and an outermost dielectric layer. The outermost inner electrode is located at an outermost position of the inner electrodes in a direction in which the inner electrodes are stacked. The outermost dielectric layer is located outside the outermost inner electrode. A proportion in which the boundary layer is present at the interface is about 69% or more. A continuity of the outermost inner electrode is about 60% or more.

Abstract: A monolithic ceramic capacitor includes an outer electrode arranged on a ceramic element body including inner electrodes, and a dielectric layer present between a pair of the inner electrodes adjacent in a stacking direction and extending to one of a pair of end surfaces of the ceramic element body that defines an inter-electrode dielectric layer. A gap extending in a direction connecting the inner electrodes sandwiching the inter-electrode dielectric layer is present in about 5% to about 90% of inter-electrode dielectric layers in the ceramic element body at a position near or adjacent to at least one of the pair of end surfaces of the ceramic element body.

Abstract: Polyimides derived from a primary aromatic diamine and aromatic dianhydride mono-mer moieties, wherein one or more of said moieties contain at least one substituent on the aromatic ring selected from propyl and butyl, especially from isopropyl, isobutyl, tert.butyl, show good solubility and are well suitable as dielectric material in electronic devices such as capacitors and organic field effect transistors.

Abstract: There is provided an array-type multilayered ceramic electronic component including: a ceramic body; a plurality of external electrodes formed on one surface of the ceramic body and the other surface thereof opposing the one surface; and a plurality of internal electrode multilayered parts formed in the ceramic body and connected to the external electrodes, respectively, wherein when a gap between the internal electrode multilayered parts is G and internal electrode density is D, 40%?D?57%, 10 ?m?G?200 ?m, and G?(0.0577×D2)?(4.4668×D)+111.22. Therefore, delamination and cracking may be prevented.

Abstract: A dielectric material is provided. The dielectric material includes at least one layer of a substantially continuous phase material. The material is selected from the group consisting of an organic, organometallic, or combination thereof in which the substantially continuous phase material has delocalized electrons.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; first and second internal electrodes provided within the ceramic body and including lead-out portions exposed to a first surface of the ceramic body and having an overlapping area, the overlapping area being exposed to the first surface of the ceramic body; external electrodes formed on the first surface of the ceramic body and connected to the respective lead-out portions; and an insulation layer formed on the first surface of the ceramic body and on third and fourth surfaces thereof connected to the first surface, wherein the lead-out portions have a predetermined interval from the third or fourth surface of the ceramic body.

Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: New polymeric dielectric materials are provided for high power capacitors, especially for mobile and weapons applications. These materials utilize aminoplast crosslinking in their polymeric structure. The aminoplast crosslinking ability of these materials allows them to be customized for a number of applications, but also allows the materials to have a higher crosslinking density, leading to higher dielectric constants, higher breakdown voltage, and higher thermal stability. These materials can be incorporated into current capacitor manufacturing schemes with little to no processing changes.

Abstract: A capacitor has first planer internal electrodes in electrical contact with a first external termination. Second planer internal electrodes are interleaved with the first planer internal electrodes wherein the second planer internal electrodes are in electrical contact with a second external termination. A dielectric is between the first planer internal electrodes and the second planer internal electrodes and at least one of the external terminations comprises a material selected from a polymer solder and a transient liquid phase sintering adhesive.

Abstract: In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.

Abstract: In this process of forming a dielectric thin film, when a dielectric thin film represented by Ba1?xSrxTiyO3 (0.2<x<0.6 and 0.9<y<1.1) is formed by a sol-gel method, the process from coating to baking is carried out 2 to 9 times, the thickness of the thin film formed after the initial baking is 20 nm to 80 nm, the thickness of each thin film formed after the second baking and beyond is 20 nm to less than 200 nm, each baking from the first time to the second to ninth times is carried out by heating to a prescribed temperature within the range of 500° C. to 800° C. at a heating rate of 1° C. to 50° C./minute in an atmosphere at atmospheric pressure, and the total thickness of the dielectric thin film is 100 nm to 600 nm.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A capacitor includes a pair of electrodes and a metalized dielectric layer disposed between the pair of electrodes, in which the metalized dielectric layer has a plurality of metal aggregates distributed within a dielectric material. The distribution is such that a volume fraction of metal in the metalized dielectric layer is at least about 30%. Meanwhile, the plurality of metal aggregates are separated from one another by the dielectric material. A method for forming a metal-dielectric composite may include coating a plurality of dielectric particles with a metal to form a plurality of metal-coated dielectric particles and sintering the plurality of metal-coated dielectric particles at a temperature of at least about 750° C. to about 950° C. to transform the metal coatings into discrete, separated metal aggregates.

Abstract: There is provided a multilayered ceramic capacitor, including a ceramic body, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body while having the dielectric layer therebetween, to form capacitance; upper and lower cover layers formed above and below the active layer; first and second external electrodes covering both end surfaces of the ceramic body; a plurality of first and second dummy electrodes extended from the first and second external electrodes; and a plurality of piezoelectric members connecting the first internal electrode and the first dummy electrode or the second internal electrode and the second dummy electrode, inside the active layer, the piezoelectric members having a higher dielectric constant than the dielectric layer.

Abstract: There are provided a multilayer ceramic electronic component and a fabricating method thereof. The multilayer ceramic electronic component includes: a multilayer ceramic body including a first ceramic powder and having a plurality of ceramic sheets stacked therein, each ceramic sheet having a thickness of 1 ?m or less; internal electrode patterns formed on the plurality of ceramic sheets; and dielectric patterns formed on the ceramic sheets to enclose the internal electrode patterns, the dielectric patterns including a second ceramic powder having a particle size smaller than that of the first ceramic powder and each having a thickness equal to or thinner than that of each of the internal electrode patterns.

Abstract: Systems and methods are provided for fabricating a thin film capacitor involving depositing an electrode layer of conductive material on top of a substrate material, depositing a first layer of ferroelectric material on top of the substrate material using a metal organic deposition or chemical solution deposition process, depositing a second layer of ferroelectric material on top of the first layer using a high temperature sputter process and depositing a metal interconnect layer to provide electric connections to layers of the capacitor.

Abstract: A method for fabricating a supercapacitor-like electronic battery includes forming a first current collectors on a substrate. A first electrode is formed on the first current collector. A first electrode is formed from a first solid state electrolyte and a first conductive material where the first conductive material is irreversible to the mobile ions contained in the first solid state electrolyte and the first conductive material exceeds the percolation limit. An electrolyte is formed on the first electrode. A second electrode is formed on the electrolyte. The second electrode is formed from a second solid state electrolyte and a second conductive material where the second conductive material is irreversible to the mobile ions contained in the second solid state electrolyte and the second conductive material exceeds the percolation limit. A second current collector is formed on the second electrode.

Abstract: An exemplary embodiment of the present invention provides a passive electrical component comprising a substrate, a first electrically conductive layer, a first dielectric layer, and a second electrically conductive layer. The first electrically conductive layer can be additively deposited on the substrate. The first dielectric layer can be additively deposited on the first conducive layer. The first dielectric layer can comprise a cross-linked polymer. The second electrically conductive layer can be additively deposited on the first dielectric layer. The resonant frequency of the passive electrical component can exceed 1 gigahertz.

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.

Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.

Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.

Abstract: An RF filter for an active medical device (AMD), for handling RF power induced in an associated lead from an external RF field at a selected MRI frequency or range frequencies includes a capacitor having a capacitance of between 100 and 10,000 picofarads, and a temperature stable dielectric having a dielectric constant of 200 or less and a temperature coefficient of capacitance (TCC) within the range of plus 400 to minus 7112 parts per million per degree centigrade. The capacitor's dielectric loss tangent in ohms is less than five percent of the capacitor's equivalent series resistance (ESR) at the selected MRI RF frequency or range of frequencies.

Abstract: A PZT-based ferroelectric thin film is formed by coating a PZT-based ferroelectric thin film-forming composition on a lower electrode of a substrate one or two or more times, pre-baking the composition, and baking the composition to be crystallized, and this thin film includes PZT-based particles having an average particle size in a range of 500 nm to 3000 nm when measured on a surface of the thin film, in which heterogeneous fine particles having an average particle size of 20 nm or less, which are different from the PZT-based particles, are precipitated on a part or all of the grain boundaries on the surface of the thin film.

Abstract: Disclosed herein is a material having formula (A3+((4-5n)/3)-?B5+n)xTi1-xO2, wherein 0<n<0.8, ? and x is such that the material has a rutile structure, 0<n<0.8, ? is between 0 and 0.025 inclusive, A3+ is a trivalent positive ion and B5? is a pentavalent positive ion. A process for making the material, and its use as a dielectric material, are also described.

Abstract: A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N3? anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO3-?)?-(ABO3-?-?N?)1-?. A represents a divalent element, B represents a tetravalent element, ? satisfies 0.005???1.0, 1-? satisfies 0.05?1-??0.9, and 1-? is an area ratio between the regions containing rich N3? anions and the matrix of remaining oxide perovskite material.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: An anchor group anchors organic dielectric compounds used in the production of organically based capacitors. The capacitors referred to are those that can be produced in a parallel process on a prepeg or other common printed circuit board substrate without additional metallisation on copper. The pre-fabricated capacitor layer can then be built into the printed circuit board, thereby gaining on space and cost for the surface of the printed circuit board.

Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: A capacitor forming unit according to one embodiment includes a dielectric plate with a plurality of through holes; a first conductor film formed on an upper surface of the dielectric plate; a first insulator film formed on the front end portion of the upper surface of the dielectric plate; a second conductor film formed on a lower surface of the dielectric plate; a second insulator film formed on the rear end portion of the lower surface of the dielectric plate; first electrode rods disposed in some of the through holes; and second electrode rods disposed in the remaining through holes where the first electrode rods are not disposed. The first electrodes are electrically connected to the first conductor film and electrically insulated from the second conductor film. The second electrode rods are electrically connected to the second conductor film and are electrically insulated from the first conductor film.

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract: A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode—dielectric—electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors.