Cordwood Type Patents (Class 361/744)
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Patent number: 5604666Abstract: The structure of an outdoor communication device includes a device body and a mounting base. The device body includes a device body, a disk-like mounting portion, a plurality of units, and a cylindrical cover. The units are enclosed in rectangular parallelepiped cases and are stacked and mounted on the mounting portion and serve to separately store electrical circuits for driving the device. The cylindrical cover has an opening portion on one end face side and serves to store the stacked units. The opening portion is fixed to the mounting portion. The mounting portion is detachably mounted on the mounting base such that the device body is suspended from and fixed to the mounting base with the mounting base being located above the device body. Fixing members are used to fix the units while the units are stacked on the mounting portion, such that the units are stacked substantially in a form of a cross.Type: GrantFiled: April 20, 1995Date of Patent: February 18, 1997Assignee: NEC CorporationInventor: Kazuhisa Yoshizawa
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Patent number: 5548486Abstract: An electrical connection pin blank having at least one compliant section is affixed to a first circuit board by compressive deformation in such a way that the compliant section of the pin blank projects outwardly from the surface of the first circuit board. The end of the pin projecting from the first circuit board is then inserted into a corresponding opening in a second circuit board and the two boards brought together until the second circuit board is firmly affixed to the complaint section of the pin by compliant pin connection.Type: GrantFiled: January 21, 1994Date of Patent: August 20, 1996Assignee: International Business Machines CorporationInventors: Stephen J. Kman, John A. Stubecki, William R. Sondej
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Patent number: 5544969Abstract: A module is sandwiched between an underlying member and a superimposed enclosure. The underlying member may be a base or another enclosure. The module is constructed so that it can be secured to the underlying member. The superimposed member has feet formed with horizontal grooves which fit into pockets in corners of the module. A slide is horizontally movable in the module between retracted position and an operative position. In the operative position edges of the slide engage in the grooves in the feet to lock the superimposed enclosure to the module and thereby to the underlying member. The slide may be detachably secured in operative position.Type: GrantFiled: August 10, 1994Date of Patent: August 13, 1996Assignee: Sun Microsystems, Inc.Inventors: James G. Ammon, John C. Nuttall
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Patent number: 5526230Abstract: A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.Type: GrantFiled: September 21, 1993Date of Patent: June 11, 1996Assignee: Thomson-CSFInventor: Christian Val
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Patent number: 5490041Abstract: A plurality of memory modules are stacked so as to form a multilayer integrated memory circuit. All of the memory modules have a plurality of bare memory IC chips mounted thereon, and have the same structure, the same circuit configuration and the same terminal arrangement in lead frames with each other. Each of the memory modules to be stacked in each layer is rotated by 90.degree., 180.degree. or 270.degree. before being stacked and connected to each other. Thus, in the multi-layered memory circuit, it is possible that signals can be selectively input/output to/from a particular layer in the multilayer structure, although the lead terminals of each of memory modules has the same configuration and the same arrangement with each other. As a result, a small-size integrated memory circuit device with a large memory-capacity can be provided, which can be fabricated easily and efficiently. A higher processing speed of digital computers can be also achieved.Type: GrantFiled: April 4, 1994Date of Patent: February 6, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hitonobu Furukawa, Hayami Matsunaga, Yoshikazu Suehiro, Masao Iwata, Takeo Yasuho, Izumi Okamoto, Kazuo Takeda, Shuji Ida
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Patent number: 5479320Abstract: A printed circuit board modular assembly is disclosed. The disclosed invention comprises a first printed circuit board having an electronic terminal portion for providing electrical connection to the first printed circuit board; a second printed circuit board having an electrical terminal portion for providing electrical connection to the second printed circuit board; a spacing member disposed between the first and second printed circuit boards; and electrical signal transmission contacts situated on the spacing member for providing electrical connection between the first printed circuit board and the second printed circuit board.Type: GrantFiled: October 20, 1993Date of Patent: December 26, 1995Assignee: Compaq Computer CorporationInventors: H. Scott Estes, James J. Ganthier
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Patent number: 5457609Abstract: A battery powered device (100) utilizing a rechargeable battery (135) comprises a ball bearing (300) having a first diameter for receiving a current and a housing (200) having an opening (405) formed therethrough in which the ball bearing (300) is situated, wherein the opening (405) has a second diameter of less than the first diameter. The battery powered device (100) further comprises a spring (305) situated in the opening (405) in contact with the ball bearing (300) and a spring cap (310) fastened to the housing (200) for forcibly holding the spring (305) in contact with the ball bearing (300). A conductive element is coupled between the spring and the rechargeable battery such that the current received by the ball bearing (300) is supplied to the rechargeable battery (135) via the spring (310).Type: GrantFiled: April 4, 1994Date of Patent: October 10, 1995Assignee: Motorola, Inc.Inventors: Vivek Bhanot, Zainal A. M. Yahya, Tai C. Thiam
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Patent number: 5450287Abstract: A semiconductor device which includes an insulating substrate having a semiconductor chip mounted on a first face thereof, and an insulating first package member fixed on the first face with surrounding the semiconductor chip. An insulating second package member is fixed on a second face of the substrate, which is opposite to the first face. The chip is housed in a first cavity formed by the substrate and the first package member. The first cavity is sealed by a first sealing member fixed on an opening end of the first package member. The first and second package members are respectively fixed on both sides of the substrate, so that the package is substantially or nearly symmetrical in structure in relation to the substrate. Thus, stresses in the substrate due to expansion and contraction thereof are almost or substantially balanced with each other in a firing or burning process, and as a result, warpage of the substrate is difficult to be generated and flatness of the mounting face of can be improved.Type: GrantFiled: July 7, 1993Date of Patent: September 12, 1995Assignee: NEC CorporationInventor: Masato Ujiie
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Patent number: 5446620Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. Moisture-barriers may be provided to upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may be constructed with one or more metal layers to prevent warpage. These level-one packages are aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors are thermally coupled to the level-two package to help dissipate heat.Type: GrantFiled: October 8, 1993Date of Patent: August 29, 1995Assignee: Staktek CorporationInventors: Carmen D. Burns, Jerry Roane, James W. Cady
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Patent number: 5440453Abstract: The invention provides a packaging technique implementing an electronic circuit, comprising several individually packaged sub-circuits, on a circuit board within the footprint of a single package. The embodiment of the present invention is particularly advantageous when implementing application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Selected pins of an upper package are electrically coupled to corresponding pins of the next lower adjacent package such that the pins of the uppermost package can be coupled to the pins of the lowermost package and correspondingly to the signal leads and power bus conductors of the printed circuit board. Portions of selected pins may be removed from one or more packages prior to forming the stacked structure to electrically isolate corresponding pins of upper packages from the pins of lower packages. A template is provided that permits rapid identification of pins to be removed before the packages are configured in the stack.Type: GrantFiled: November 12, 1993Date of Patent: August 8, 1995Assignee: Crosspoint Solutions, Inc.Inventors: Laurance H. Cooke, Matthew D. Penry
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Patent number: 5435734Abstract: A system for directly connecting one integrated circuit to another achieved by depositing gold onto the bonding pads of both integrated circuits, aligning the respective bonding pads and biasing both circuits into gas-tight, electrically conductive relation through the use of an initial compression force and a spring assembly. The gold bumps deposited on the bonding pads include ridges to ensure an optimal gas-tight seal. Alignment posts are also inserted through the host integrated circuit, which match notches cut into the periphery of the target integrated circuit, to ensure proper polarization and mating of the bonding pads of each integrated circuit. The integrated circuits and spring assembly are housed, and thus held together by, a carrier assembly. The carrier assembly also serves to dissipate heat generated by the integrated circuits, adapts for mounting on a printed circuit board, and includes a ferrule over an optical sensing area provided on the host integrated circuit.Type: GrantFiled: May 4, 1993Date of Patent: July 25, 1995Inventor: Vincent Chow
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Patent number: 5434745Abstract: Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge.Type: GrantFiled: July 26, 1994Date of Patent: July 18, 1995Assignee: White Microelectronics Div. of Bowmar Instrument Corp.Inventors: Hamid Shokrgozar, Leonard Reeves, Bjarne Heggli
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Patent number: 5430617Abstract: A modularized electronic system such as notebook or palmtop computer for packaging and assembling one or more electronic I/O module assemblies comprises one upper case assembly and one lower case assembly for mounting the I/O modules in between. Each I/O module comprises a module head and a substantially rectangular module body. The module head further comprises a rigid module connector on its bottom, vertically plugged in a receptacle on the lower case assembly. The module body further comprises a substantially rectangular protruding port on its rear end. The lower case assembly further comprises a U-shaped side opening wherein the rear protruding port of the module body engages and securely attaches to the U-shaped side opening. The I/O module is upwardly supported by the lower case assembly over the module head and the rear protruding port only.Type: GrantFiled: February 4, 1993Date of Patent: July 4, 1995Inventor: Winston Hsu
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Patent number: 5426564Abstract: A modularized electronic system for packaging and assembling one or more electronic module assemblies comprising at least one external enclosure case having one internal room for module mounting. The external enclosure case further comprises at least one upper case assembly and one lower case assembly for clamping the electronic modules in between. Each electronic module comprises a module head and a substantially rectangular module body. The module head further comprises a rigid module connector on its bottom vertically plugged in a receptacle on the lower case assembly. The module body further comprises a substantially flat top end and bottom end and is clamped between upper and lower case assemblies whereby the module assembly can be easily installed or removed by hand without using tools. The internal mounting mechanism of the system greatly simplifies the mounting mechanisms of both the internal modules and the external enclosure case and allows complete modularization of a portable computer system.Type: GrantFiled: October 21, 1992Date of Patent: June 20, 1995Inventor: Winston Hsu
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Patent number: 5424920Abstract: An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.Type: GrantFiled: April 25, 1994Date of Patent: June 13, 1995Assignee: Irvine Sensors CorporationInventor: Michael K. Miyake
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Patent number: 5394300Abstract: In an IC memory card, sub-modules, in each of which a plurality of memory ICs are mounted on each of two opposed surfaces of a sub-substrate, are mounted on each of two opposed surfaces of a single substrate. Since the number of substrates connected to a connector is one, soldering of the connector is facilitated, and the structure of the connector can be simplified. Furthermore, in an IC memory card, the sub-modules may be mounted on the substrate in such a manner that they are stacked in two stages at an opening in the substrate. In this way, the thickness of the IC memory card can be minimized. Also, the use of the die bonding process makes connection between the sub-module and the substrate easy.Type: GrantFiled: January 11, 1993Date of Patent: February 28, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshimasa Yoshimura
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Patent number: 5371654Abstract: The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection electrically interconnecting each assembly. The electrical interconnection formed from an elastomeric interposer having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection is disposed over the array of electronic devices so that the electrical interconnection between adjacent electronic devices.Type: GrantFiled: October 19, 1992Date of Patent: December 6, 1994Assignee: International Business Machines CorporationInventors: Brian S. Beaman, Fuad E. Doany, Keith E. Fogel, James L. Hedrick, Jr., Paul A. Lauro, Maurice H. Norcott, John J. Ritsko, Leathen Shi, Da-Yuan Shih, George F. Walker
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Patent number: 5355282Abstract: An object of the present invention is to provide a connector structure for achieving a signal connection between modules not by way of a motherboard. In an electronic apparatus in which a plurality of modules (3, 4) are mounted on a motherboard (1) in an orderly manner, while flatly positioned parallel to the latter, and electrical connections between the modules and between the respective module and the motherboard are achieved by a connector body (2) extending along a boundary between the adjacent modules (3, 4), contacts (6, 7) are provided in the peripheral regions of the respective module (3, 4). Both the contacts (6, 7) are electrically connected with each other by pressing a connector spring (8) fixed in the connector body (2) onto the contacts (6, 7) provided in the peripheral regions of the adjacent modules (3. 4).Type: GrantFiled: April 26, 1993Date of Patent: October 11, 1994Assignee: Fujitsu LimitedInventors: Hitoshi Yokemura, Masao Hosogai, Yuko Tsujimura
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Patent number: 5353191Abstract: A unitary heat sink and connector housing (10, 10', 10", 10"') is disposed between a pair of electrical members, such as printed circuit boards (11, 12, 31) and/or flexible etched circuits (32) in an overall assembly used in a variety of high-performance miniaturized electronic products. One or more flexible electrical connectors (21, 25, 26, 29, 30) are mounted within the unitary heat sink and connector housing (10, 10', 10", 10"') and provide a circuit interface between respective circuit elements or pads (13, 14) on the printed circuit boards (11, 12, 31) and/or flexible etched circuits (32), respectively. The unitary heat sink and connector housing (10, 10', 10", 10"'), which preferably has heat-radiating fins (20), is made from a material which is thermally conductive but electrically non-conductive. Examples of such a material are anodized aluminum, silicon dioxide and beryllium oxide. Any suitable ceramic material could be used.Type: GrantFiled: March 8, 1993Date of Patent: October 4, 1994Assignee: The Whitaker CorporationInventors: Keith L. Volz, Frederick R. Deak, David C. Johnson, Warren A. Bates, Robert M. Renn
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Patent number: 5343366Abstract: This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures.Type: GrantFiled: June 24, 1992Date of Patent: August 30, 1994Assignee: International Business Machines CorporationInventors: Thomas M. Cipolla, Paul W. Coteus, Ioannis Damianakis, Glen W. Johnson, Peter G. Ledermann, Linda C. Matthew, Lawrence S. Mok
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Patent number: 5343075Abstract: A composite semiconductor device comprises a multilayer wiring board, a plurality of resin-sealed semiconductor devices having external leads projecting from the opposite sides thereof and stacked one on another, on a multilayer wiring board, and contact plates provided with wiring lines on the inner surfaces thereof and disposed close to the opposite sides of the resin-sealed semiconductor devices, respectively, with the wiring lines in electrical contact with the external leads of the resin-sealed semiconductor devices, respectively. Since the resin-sealed semiconductor devices are stacked, the degree of integration of the resin-sealed semiconductor devices is multiplied by the number of the resin-sealed semiconductor devices so stacked. Since the resin-sealed semiconductor devices are electrically interconnected by the wiring lines of the contact plates, the multilayer wiring board need not be provided with any wiring for electrically interconnecting the resin-sealed semiconductor devices.Type: GrantFiled: June 22, 1992Date of Patent: August 30, 1994Assignee: Sony CorporationInventor: Tomoki Nishino
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Patent number: 5334875Abstract: There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.Type: GrantFiled: March 2, 1993Date of Patent: August 2, 1994Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.Inventors: Toshio Sugano, Kohji Nagaoka, Seiichiro Tsukui, Yoshiaki Wakashima, Michio Tanimoto, Masayuki Watanabe, Suguru Sakaguchi, Kunihiko Nishi, Aizo Kaneda, Kohji Serizawa, Michiharu Honda, Tohru Yoshida, Takeshi Komaru, Atsushi Nakamura
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Patent number: 5335146Abstract: A high density interconnection technique for connecting large numbers of unique signal lines between orthogonally positioned circuit cards, utilizes pins from the back of a zero insertion force connector (ZIF) to extend through the interconnection card and mate with a female socket connector on a second circuit board. Pins from the ZIF connector which are not aligned with the sockets of the orthogonally positioned socket connector may be connected to pins on the interconnection card which are aligned with the socket connector but not the ZIF. Very high numbers of connections between circuit cards may be made in a small volume and maintain signal line length at a minimum to ensure maximum signal transfer speed.Type: GrantFiled: January 29, 1992Date of Patent: August 2, 1994Assignee: International Business Machines CorporationInventor: Robert F. Stucke
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Patent number: 5331514Abstract: An object to the present invention is to provide an integrated-circuit package in which crosstalk can be reduced and impedance matching can be made. According to the present invention, conductive poles are grid-like arranged equidistantly in rows respectively in the vertical and transversal directions of an insulating substrate. The conductive poles are classified into signal conductive poles which are electrically connected to electrodes of the integrated circuit and the mother board, and earthed ground conductive poles arranged so as to adjacently surround the signal conductive poles.Type: GrantFiled: August 3, 1992Date of Patent: July 19, 1994Assignee: NGK Spark Plug Co., Ltd.Inventor: Masao Kuroda
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Patent number: 5331516Abstract: The present invention makes it easier to connect board modules to each other and to increase reliability in a portable semiconductor apparatus having two board modules within a frame. Upper-row connection pins and lower-row connection pins have electrode leads, each having connection portions divided into two parts that are arranged in respective upper and lower rows. One of the board modules is inserted between one upper-row electrode lead and one lower-row electrode lead and electrically connected. The other board module is inserted between another upper-row electrode lead and another lower-row electrode lead and electrically connected. In this way, the board modules are electrically connected to each other.Type: GrantFiled: January 8, 1993Date of Patent: July 19, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takayuki Shinohara, Masatoshi Kimura
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Patent number: 5311404Abstract: An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.Type: GrantFiled: June 30, 1992Date of Patent: May 10, 1994Assignee: Hughes Aircraft CompanyInventors: Philip A. Trask, Vincent A. Pillai, Thomas J. Gierhart
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Patent number: 5311401Abstract: Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.Type: GrantFiled: July 9, 1991Date of Patent: May 10, 1994Assignee: Hughes Aircraft CompanyInventors: Louis E. Gates, Jr., Richard K. Cochran
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Patent number: 5309327Abstract: A circuit board assembly system for manufacturing a prototype printed circuit board having a matrix formed in it. A base board having a connection matrix that matches the matrix of the printed circuit board is hinged to a frame having tracks for receiving the printed circuit board, so that the printed circuit board is locatable in a fixed position in relation to the printed circuit board with their respective matrices matching. Component leads may be inserted into the connection matrix through the printed circuit board to form a circuit, which may be tested. The base board may be pivoted away from the printed circuit board to allow the leads to be soldered. The printed circuit board may then be removed from the base board. A cover that is latchable onto the printed circuit board may be used to prevent components from being accidentally removed from the printed circuit board.Type: GrantFiled: November 30, 1992Date of Patent: May 3, 1994Assignee: Platform Systems Inc.Inventor: Cody Z. Slater
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Patent number: 5303120Abstract: A method of manufacturing inversion ICs includes the steps of connecting a first electrode pad group of a semiconductor chip to a second lead group via wires, connecting a second electrode pad group of the semiconductor chip to a first lead group via wires, sealing the semiconductor chip, the first and second lead groups, and the wires in a resin so that the outer lead portions of the leads are exposed, and bending the outer lead portions of the leads toward the bottom surface of the semiconductor chip.Type: GrantFiled: October 2, 1992Date of Patent: April 12, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Hiroshi Seki
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Patent number: 5303119Abstract: The invention concerns a carrier for Integrated Circuits (ICs). The ICs are carried by a multi-layer board, constructed of individual layers. Some layers carry conductive traces, and the traces are connected together to form a 3-dimensional network connecting the ICs. The individual layers are constructed of a flexible material, which is commercially available in large sheets, thus allowing multiple copies of the trace patterns to be printed simultaneously. The multi-layer board is attached to a standard printed circuit board, by pins which are driven through them both, and soldered into place.Type: GrantFiled: May 11, 1993Date of Patent: April 12, 1994Assignee: NCR CorporationInventor: Johan O. Hilbrink
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Patent number: 5301089Abstract: Disclosed is an improved parallel processing system using a radial bus assembly comprising a stack of disks each having an integrated circuit crossbar switch fixed at its center, a plurality of communication lines of equal length radially extending from the communication terminals of the crossbar switch and terminating on the circumference of the disk, a plurality of control lines each being arranged between adjacent communication lines, and radially extending from the control terminals of the crossbar switch and terminating short of the circumference of the disk, and male-and-female joints to electrically connect the terminations of the control lines of all disks in terms of same angular positions longitudinally in common.Type: GrantFiled: April 17, 1992Date of Patent: April 5, 1994Assignee: Graphico Co., Ltd.Inventor: Tokuhei Takashima
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Patent number: 5283712Abstract: An integrated circuit for a vehicle, vehicle which is formed in the shape of a case and which includes a pair of circuit boards, and a connector electrically connected to another connector. Each circuit board includes a metal circuit board main body, defining an outer portion of the case, an insulating layer formed on the entire inner surface of the circuit board main body, a conductive layer formed on the insulating layer in a predetermined circuit pattern, and a plurality of circuit elements electrically connected to a predetermined portion of the conductive layer.Type: GrantFiled: August 4, 1992Date of Patent: February 1, 1994Assignee: Mazda Motor CorporationInventors: Osamu Michihira, Tomoji Izumi, Nagahisa Fujita, Yuichi Itoh, Masaaki Shimizu, Seiji Hirano
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Patent number: 5280408Abstract: A transformer apparatus whose transformer and a plurality of circuit-breakers are individually accommodated in a plurality of different casings. The casings are stacked one above each other in a plurality of stages with gaps between two subsequent casings and between the casing in the lowermost stage and the floor surface on which the apparatus is mounted. When a specific casing among the plurality of casings which is in an intermediate stage is to be dismounted, support columns are disposed on the outside of the specific casing with their respective ends inserted into the relevant gaps in such a manner that the support columns support the upper subsequent casing, thereby enabling the intermediate casing to be dismounted and remounted.Type: GrantFiled: May 15, 1992Date of Patent: January 18, 1994Assignee: Hitachi, Ltd.Inventors: Toshiaki Izumi, Tooru Tanimizu
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Patent number: 5278728Abstract: A mounting assembly for a plurality of bipolar electrical components connected between two generally parallel electrical supports, each bipolar electrical component having a lower base terminal fixedly mounted to the first electrical support and a generally flat upper terminal having a random angular orientation about the central axis of the electrical components, an electrically conducting coupler which telescopically receives the upper terminal of the component to form a rigid electrical connection between the coupler and an electrical component at one end of the coupler and the other end of the coupler is electrically connected to the second electrical support.Type: GrantFiled: June 25, 1992Date of Patent: January 11, 1994Assignee: The Lincoln Electric CompanyInventors: George D. Blankenship, Kenneth L. Justice
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Patent number: 5268819Abstract: A printed circuit board upon which are mounted a number of electronic components is provided with a connector strip for electrically coupling the components to respective components on a second circuit board located underneath. The strip comprises a body portion and pins projecting thereform. The pins have a stepwise configuration with a first end portion extending through apertures in the upper circuit board and connected to a second connector strip on the second circuit board, a second end portion extending through the body portion, and a middle portion which abuts the surface of the upper circuit board and by which the strip is connected to the upper circuit board by means of a solder joint. Components on the upper circuit board are electrically coupled by means of tracks which are connected to the components at one end by a solder joint and at the other end by a solder joint, via pins, to the second connector strip and tracks on the lower circuit board.Type: GrantFiled: March 9, 1992Date of Patent: December 7, 1993Assignee: Nokia Mobile Phones Ltd.Inventor: Pekka S. Lonka
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Patent number: 5258891Abstract: Multichip module is provided with standard wiring layers comprising standardized wiring patterns, a custom wiring layer comprising customized wiring patterns and chip mounting pads, a plurality of antifuses which are positioned in standardized installation positions and each of which provides the possibility of defining the presence or absence of an electrical connection between a specified conductive track of a standard wiring layer and a specified conductive track of the custom wiring layer, and a plurality of wafer chips which are electrically connected to the chip mounting pads and mounted on the chip mounting pads, whereby disadvantages of hybrid integrated circuits are overcome while offering numerous advantages of hybrid integrated circuits.Type: GrantFiled: November 26, 1991Date of Patent: November 2, 1993Assignee: Kawasaki Steel CorporationInventor: Norimitsu Sako
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Patent number: 5253143Abstract: A housing for an electronic circuit, in particular for an electronic control circuit of a motor vehicle internal combustion engine has a circuit accommodation area, a connection area, a distribution area, and a connection device for a separable electrical connection of information and supply leads. The housing has two housing parts which are separable from one another and include a first housing part having accommodating area and a second housing part having the connection area for the connection device and having the distribution area. A dividing part separates the connection area and the distribution area. Contact connections for the connection device are provided on the dividing part. The first housing part has a base wall which in a closed condition of the housing closes the second housing part.Type: GrantFiled: February 5, 1992Date of Patent: October 12, 1993Assignee: Robert Bosch GmbHInventors: Herbert Klinger, Gerhard Thomas, Karl Wutz
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Patent number: 5253146Abstract: An earthed intermediate frame (2) fitted between circuit boards (1) is provided with through apertures (8) for connectors (4) connecting the circuit boards (1), and grooves (6) are provided in register with the signal runs (5) on the surface of the circuit board (1), located on the surface of the intermediate frame (2) placed against the surface of the circuit board. The intermediate frame made of a metal or the surfaces of the apertures (8) surrounding the connectors (4) connecting the circuit boards (1) and of the grooves (6) covering the signal runs (5) of the circuit board (1) have been coated with an earthed metal folio (7).Type: GrantFiled: December 5, 1991Date of Patent: October 12, 1993Assignee: Nokia Mobile Phones Ltd.Inventors: Mikko Halttunen, Petteri Vanhanen
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Patent number: 5251099Abstract: A high-density electronics package (10) that houses a plurality of circuit cards (21,22,25,26), heat sinks (23,27) and circuit interconnections (33) in a single housing (12). The electronics package (10) uses conical shaped interfaces for locating and locking components, which greatly enhances the serviceability, thermal management and strength of the electronics package (10). Assembly is accomplished by using a selected conical angle on a first heat sink (23) that mates with a matching conical surface (13) on the housing (12). A second heat sink (27) has a conical angle (located in the opposite direction of the conical angle of the first heat sink) that mates with an identical angle on an expandable wedge ring (31) used for positioning purposes.Type: GrantFiled: August 14, 1992Date of Patent: October 5, 1993Assignee: Hughes Aircraft CompanyInventors: Steven R. Goss, Owen H. Taggart
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Patent number: 5251106Abstract: An electronic system having a plurality of electronic devices contained in a plurality of stackable enclosures is provided. Each of the plurality of stackable enclosures is stackable and interlockable together with another one of the plurality of stackable enclosures. Each of the plurality of stackable enclosures comprises a housing having a top surface and a bottom surface. A first plurality of projections are provided to extend upwardly from the top surface. The first plurality of projections are spaced to define a first group of grooves therebetween. A second plurality of projections are provided to extend downwardly from the bottom surface. The second plurality of projections are spaced to define a second group of grooves therebetween. Each of the second group of grooves corresponds to a respective one of the first plurality of projections. Each of the first group of grooves corresponds to a respective one of the second plurality of projections.Type: GrantFiled: March 6, 1992Date of Patent: October 5, 1993Assignee: Everex Systems, Inc.Inventor: John T. Hui
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Patent number: 5249098Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.Type: GrantFiled: July 28, 1992Date of Patent: September 28, 1993Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Tom Ley
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Patent number: 5247423Abstract: A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.Type: GrantFiled: May 26, 1992Date of Patent: September 21, 1993Assignee: Motorola, Inc.Inventors: Paul T. Lin, Michael B. McShane
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Patent number: 5241454Abstract: An electronic package which includes a rigid first substrate (e.g., ceramic) having a plurality of conductive pins spacedly located therein. These pins each include one end portion extending below an undersurface of the substrate for positioning and electrically coupling within a second substrate (e.g., printed circuit board), while also including an opposite end portion which projects from an opposite, upper surface of the first substrate. These upwardly projecting end portions are designed for accommodating, in stacked orientation, a plurality of thin film, flexible circuitized substrates thereon, each of these substrates being electrically coupled to a respective pin, if desired, using a solder composition.Type: GrantFiled: January 22, 1992Date of Patent: August 31, 1993Assignee: International Business Machines CorporationInventors: Joseph G. Ameen, Joseph Funari, David W. Sissenstein, Jr.
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Patent number: 5241456Abstract: An improved high density interconnect structure may include electronic components mounted on both sides of its substrate or a substrate which is only as thick as the semiconductor chips which reduces the overall structure thickness to the thickness of the semiconductor chips plus the combined thickness of the high density interconnect structure's dielectric and conductive layers. In the two-sided structures, feedthroughs, which are preferably hermetic, provide connections between opposite sides of the substrate. Substrates of either of these types may be stacked to form a three-dimensional structure. Means for connecting between adjacent substrates are preferably incorporated within the boundaries of the stack rather than on the outside surface thereof.Type: GrantFiled: July 2, 1990Date of Patent: August 31, 1993Assignee: General Electric CompanyInventors: Walter M. Marcinkiewicz, Charles W. Eichelberger, Robert J. Wojnarowski
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Patent number: 5241450Abstract: A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.Type: GrantFiled: March 13, 1992Date of Patent: August 31, 1993Assignee: The United States of America as represented by the United States Department of EnergyInventors: Anthony F. Bernhardt, Robert W. Petersen
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Patent number: 5239448Abstract: A method of reducing the area of MCMs that are integral to a flexible carrier is provided. A locally complex area, i.e. multilayer MCM carrier is constructed on a flex carrier, along with other components to form a subsystem. The flex carrier provides the interface between the MCM and the system that is utilizing the function. Also, the flex carrier will receive non-complex portions of the function, e.g. low I/O devices, not required to be mounted on the complex area (MCM) of the subsystem. The locally complex functional area will contain the high performance DCA mounted components, such as custom ASICs, processors, high frequency analog parts and other high I/O chips. The MCM on flex is constructed by obtaining an appropriate flexible carrier, such as a dielectric material having electrically conductive signal lines circuitized on both sides.Type: GrantFiled: October 28, 1991Date of Patent: August 24, 1993Assignee: International Business Machines CorporationInventors: Charles T. Perkins, Gustav Schrottke
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Patent number: 5239447Abstract: An electronic device packaging structure is described wherein an electronic device is electrically connected to a substrate wherein the electronic device subtends a non-normal angle with respect to the substrate. In a more specific embodiment, a plurality of electronic devices are stacked at offset with respect to each other to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. This surface is disposed against a substrate having a plurality of contact locations thereon. The electronic device contact locations can be electrically interconnected to the substrate contact locations by solder mounds or alternatively by a cylindrical shaped elastomeric body having metallization bands with a spacing corresponding to the electronic device contact locations.Type: GrantFiled: September 13, 1991Date of Patent: August 24, 1993Assignee: International Business Machines CorporationInventors: Paul W. Cotues, Paul A. Moskowitz, Philip Murphy, Mark B. Ritter, George F. Walker
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Patent number: 5233505Abstract: A security device for protecting electronically-stored data comprising a protected circuit board which has a memory device for storing data code and a battery, a plurality of protective circuit boards respectively overlaid on each side of the protected circuit board, and a plurality of connectors connected between the protected circuit board and the protective circuit boards, wherein the printed circuit on each protective circuit board is respectively connected to the printed circuit on the protected circuit board forming into a series electronic circuit. Detaching either protective circuit board from said protected circuit board or damaging either protective circuit board will break the series electronic circuit causing any code data stored in the memory device to be erased.Type: GrantFiled: December 30, 1991Date of Patent: August 3, 1993Assignee: Yeng-Ming ChangInventors: Yeng-Ming Chang, Wing-Fai Chun