With Specific Connection Material Patents (Class 361/779)
  • Publication number: 20040177996
    Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a substrate having contactors on a first side and pads on a second side; (b) a card having pads on a first side; and (c) interconnectors that electrically connect the pads on the second side of the substrate with the pads on the card; wherein at least one of the interconnectors includes at least a portion that does not melt at temperatures in a range from about 183° C. to about 230° C., and the distance between the substrate and the card is determined by a dimension of the at least a portion.
    Type: Application
    Filed: April 16, 2003
    Publication date: September 16, 2004
    Applicant: Nexcleon, Inc.
    Inventors: Konstantine N. Karavakis, Tom T. Nguyen
  • Patent number: 6774314
    Abstract: An electronic device assembled using a coupler which has an electroconductive region and a resin region on the surface. Flexibility of the resin region absorbs stress caused by difference in thermal expansion coefficient between an organic printed circuit board and a semiconductor chip through the deformation of the electroconductive region. As a result, formation of cracking in the coupler is avoided. It is preferable that the resin region occupies from 20 to 80% of the total surface area of the coupler. The coupler may be formed from a molten blend of the heat resistant resin and a joining metal. The coupler may also be formed by molding a blend of the heat resistant resin and metal powder, wherein the metal powder locating on the surface of the coupler have a joining metal joined thereto.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: August 10, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiyuki Toyoshima, Suguru Nagae
  • Patent number: 6697261
    Abstract: Conductive or solder bumps are stacked between a mounted component such as a BGA device and a printed wiring substrate in a multileveled printed circuit board unit. An interposer or relay substrate is interposed between the adjacent stacked conductive bumps. The interposer substrate is made of a porous material. When any difference in the expansion is caused between the printed wiring substrate and the mounted component, one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force. A shearing stress is induced in the interposer substrate. Deformation of the porous material serves to absorb the shearing stress in the interposer substrate. The conductive bumps bonded on one side of the interposer substrate as well as the conductive bumps bonded on the other side of the interposer substrate may be relieved from a shearing stress.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: February 24, 2004
    Assignee: Fujitsu Limited
    Inventor: Shinji Matsuda
  • Patent number: 6660942
    Abstract: A wiring substrate equipped with a rerouted wiring having one end connected to an electronic-part mounting pad for electrically connecting an electronic part and another end connected to an external-connection terminal. In the wiring substrate, a low-elasticity underlayer made of a material having a lower modulus of elasticity than that of a base material of the wiring substrate is disposed between the base material of the wiring substrate and each of the electronic-part mounting pad and the rerouted wiring. A method of manufacturing the wiring substrate and a semiconductor device using the wiring substrate are also disclosed.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: December 9, 2003
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Takashi Kurihara
  • Patent number: 6643142
    Abstract: A module (1) for contactless communication includes a plurality of electrical components (4, 5, 6, 7, 8) which each have at least two contact faces (9, 10, 11, 12, 13, 14, 15, 16) for the electrical connection. The electrical components (4, 5, 6, 7, 8) of the module are mounted both on a component side (MB) and an on adhesive side (MK) of a lead frame (M) formed by metal strips (MS). During the manufacture of the module (1) the metal strips (MS) of the lead frame (M) are held in one plane (E) and in position by means of an adhesive tape (K). The adhesive tape (K) has openings (A1, A2, A3, A4, A5, A6) at given positions of the lead frame (M) so as to enable electrical components to be mounted on the adhesive side (MK) of the lead frame (M).
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: November 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Gunter Aflenzer, Joachim Heinz Schober, Marcus Toth
  • Patent number: 6617529
    Abstract: In a circuit board having lands 2 each of which has a through hole 4 through which a lead of an electrical part is inserted, the lead 3 and the land 2 being mounted in the circuit board by using lead-free solder 6, the width of the land 2 corresponding to the difference in radius between the land 2 and the through hole 4 is set to about 0.40 mm or more. The width of the land 2 is set to such a value that the land exfoliation due to the solidification/shrinkage of the lead-free solder 6 and the shrinkage of the circuit board in the thickness direction can be prevented. The circuit board 1 has circuit wires at least on both the surface and the back surface.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 9, 2003
    Assignee: NEC Corporation
    Inventors: Naomi Ishizuka, Akihito Matsumoto, Eiichi Kono, Motoji Suzuki, Akihiro Sato, Hiroshi Matsuoka, Masafumi Kanai
  • Patent number: 6610430
    Abstract: A method of soldering a ball grid array device onto a circuit board which includes: positioning a solder paste brick on top of a contact pad of the circuit board, said solder past brick defining an irregularly shaped structure such that a majority of a top surface of the solder paste brick is not in contact with the solder ball terminal, wherein volatized flux gases formed during heating escape via the top surface without migrating upwardly into the solder ball terminal; attaching the ball grid array device onto the circuit board such that a solder ball terminal of the ball grid array device makes contact with a portion of an edge of the solder paste brick while remaining substantially aligned with a center of the pad; and heating the ball grid array device and the circuit board so as to melt the solder ball terminal and the solder paste brick, thereby forming a solder joint between the ball grid array device and the circuit board.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: August 26, 2003
    Assignee: Plexus Services Corp.
    Inventor: Curtis C. Thompson, Sr.
  • Patent number: 6574113
    Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gregg J. Armezzani, Matthew A. Heller
  • Patent number: 6555759
    Abstract: An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: April 29, 2003
    Inventors: George Tzanavaras, Mihalis Michael
  • Patent number: 6555760
    Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventor: Jimmy Grant Foster, Sr.
  • Patent number: 6528889
    Abstract: An electronic circuit device has an insulating substrate and an integrated circuit having a surface disposed opposite to and confronting a surface of the insulating substrate to form a gap therebetween. An adhesive material is disposed in the gap between the insulating substrate and the integrated circuit. Bumps project from the surface of the integrated circuit towards the surface of the insulating substrate. Electrode patterns are electrically connected to the bumps to electrically connect the integrated circuit to the electrode patterns. An adhesion-reinforcing pattern is spaced-apart from and surrounded by the electrode patterns. The adhesion-reinforcing pattern is disposed on a portion of the surface of the insulating substrate confronting a portion of the surface of the integrated circuit from which the bumps do not project.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: March 4, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Tsutomu Matsuhira, Atsushi Endo
  • Patent number: 6526654
    Abstract: The method comprises forming a plurality of wiring pattern layers on the front surface of a substrate. In the process of forming the wiring pattern layers, an insulator protection film keeps covering over the wiring pattern on the back surface of the substrate. When the formation of the wiring pattern layers has been completed on the front surface of the substrate, a penetrating hole is bored in the cured or hardened insulator protection film. The penetrating hole may be utilized as a conductive via or a conductive through hole. A wiring pattern layer is then formed over the hardened insulator protection film on the back surface of the substrate. It is possible to omit an additional process for removing the insulator protection film. The method contributes to further facilitation of production process and further reduction in production cost.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Zhiyi Song, Kiyokazu Moriizumi, Kazuaki Satoh, Norikazu Ozaki
  • Patent number: 6519161
    Abstract: A packaged electronic circuit using molded plastics, Thick Film, and Polymer Thick Film technology, and achieving shielding of the circuitry and components of the package. In this invention at least one of electronic devices in the package is supported in a molded pocket in the molded substrate, and circuit traces are added to the surface of the substrate and the electronic device, simultaneously creating the circuit traces and making the interconnections with the components at the same time. Shielding, which is optional, can easily be printed over the planar surface of the circuit traces and components.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: February 11, 2003
    Inventor: William J. Green
  • Patent number: 6515233
    Abstract: Disclosed is a method of producing a flexible circuit board having gold selectively plated on only desired elements of the conductive circuits. These desired elements typically are attachment sites, such as wire bond pads or ball grid array pads, for semiconductor chips. This method eliminates the requirement to buss all circuits to a common plating contact by using a background seed metal for plating continuity. This method also provides a means to alleviate the requirement for precise registration or alignment when multiple photoresist layers are employed in order to selectively plate only a portion of the metallic elements present on the flexible circuit board. The defect of resist lifting followed by nickel/gold underplating is eliminated by conditioning the intermediate photoresist to survive the nickel/gold plating bath.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: February 4, 2003
    Inventors: Daniel P. Labzentis, Francesco F. Marconi, Allan R. Knoll, David J. Bajkowski
  • Publication number: 20030016509
    Abstract: A flat circuit device without another terminals can be connected with a connector; an insulator 4 includes a bent portion 7 and a laminated portion of a first and a second insulators 5, 6 forming the bent portion 7, and ends of a first conductor 2 and a second conductor 3 extend straightly at the bent portion 7 along a curved surface of the bent portion. Thereby, the first conductor 2 and the second conductor 3 are formed straightly in parallel on an outer surface of the bent portion 7 so that the bent portion 7 performs as a connecting terminal.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 23, 2003
    Inventor: Masashi Tsukamoto
  • Patent number: 6507122
    Abstract: An integrated circuit chip package wherein the chip is encapsulated prior to mechanical bonding to a packaging substrate. The package provides a continuous adhesive interface between the encapsulated chip and surrounding encapsulant, and the substrate. This structure eliminates discontinuities in flatness and their associated stress states resulting in more reliable package contacts.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventor: Edmund D. Blackshear
  • Patent number: 6501663
    Abstract: A three-dimensional interconnect system is disclosed. The interconnect system electrically connects electrical devices that are disposed on different physical planes. The interconnect system includes a plurality of contiguously interconnected electrically conductive droplets such as solder ball droplets produced by a print-on-demand solder jet system. An interconnect is formed by repeatedly ejecting the conductive droplets along a predetermined path between components to be connected. Each ejected droplet is disposed adjacent to another ejected droplet to form a contiguously linked chain of droplets that bridge a physical gap between the components. A non-conductive coating can be deposited on the interconnect to protect the interconnect from damage and to encase the interconnect. The electrical resistance of the interconnect can be reduced by reflowing the droplets that form the interconnect, whereby the coating that encses the interconnect is operative to maintain the shape of the interconnect after reflow.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: December 31, 2002
    Assignee: Hewlett Packard Company
    Inventor: Alfred I-Tsung Pan
  • Patent number: 6498308
    Abstract: A semiconductor module includes a chip formed with an integrated circuit, a first external connecting terminal electrically connected to the integrated circuit, a printed wiring board having a second external connecting terminal, and a conductive material electrically connecting the first external connecting terminal with the second external connecting terminal, wherein the conductive material is formed so as to cover a sidewall of the second external connecting terminal. Accordingly, a semiconductor module is provided that can avoid an inferior connection caused by a crack between the lead and the pad.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: December 24, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Sakamoto
  • Patent number: 6490170
    Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: December 3, 2002
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Yoji Mori
  • Patent number: 6483039
    Abstract: A substrate of a semiconductor package is proposed, which is formed with a strip copper layer on a core layer of the substrate, wherein a solder mask is arranged to cover the core layer and two lengthwise sides of the copper layer by a width between 0.1 mm to 1.0 mm, while a surface between the sides of the copper layer is exposed by forming a groove opening to the atmosphere and plated with gold. This makes bulges generated by shrinkage of the solder mask covering the sides of the copper layer extend outwardly in a direction away from the groove opening, allowing clamping force to be sufficiently exerted on the substrate by a mold during an encapsulation process. As such, after completing the encapsulation process, an encapsulating resin remained in the runner can be easily removed without damaging the substrate, and also resin flash can be prevented from occurrence.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: November 19, 2002
    Assignee: Siliconware Precision Industries, Co., Ltd.
    Inventors: Chien-Ping Huang, Tzong-Da Ho, Chen-Hsu Hsiao
  • Patent number: 6479763
    Abstract: A conductive paste containing: conductive particles; foamable material which foams at the time of heating or decompression; and resin; characterized in that even after foaming of the foamable material, conductivity is maintained.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 12, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Emiko Igaki, Masakazu Tanahashi, Takeshi Suzuki
  • Patent number: 6479755
    Abstract: A printed circuit board and a pad apparatus having a solder deposit formed on the pad apparatus by using a mask having a slit are provided. The slit has the same shape as the solder deposit. The solder deposit includes first and second end portions individually shaped and sized to completely cover at an end portion of the pad a predetermined area of an end portion of the pad, the area defined by both the entire width of the pad and a predetermined length from the end of the pad. A connection web extends between the two end portions to integrate the two end portions into a single structure and is a longitudinal part having a width smaller than any one of both the width of the pad and the width of each of the two end portions. First and second trapezoidal portions are respectively formed at junctions between opposite ends of said connection web and one of the two end portions. The mask has a slit formed at a position corresponding to the position of the solder deposit.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: November 12, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeng-Il Kim, Gun-Yong Lee, Kwang-Soo Jung
  • Patent number: 6476503
    Abstract: A semiconductor device including a semiconductor chip sealed with an encapsulating resin. Columnar electrodes are connected to electrode pads of the semiconductor chip, and extend through the encapsulating resin. The columnar electrodes are made from bonding wires and include enlarged outer ends. Solder balls are arranged on the surface of the encapsulating resin and connected to the outer ends of the columnar electrodes. In another example, pin wires are formed by half-cutting bonding wires, bonding one end of each of the bonding wires, and cutting the bonding wires at the half-cut portions.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: November 5, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazuyuki Imamura, Yasunori Fujimoto, Masaaki Seki, Tetsuya Fujisawa, Mitsutaka Sato, Ryuji Nomoto, Junichi Kasai, Yoshitaka Aiba, Noriaki Shiba
  • Patent number: 6449168
    Abstract: The present invention refers to circuit board (10), in particular a multilayer circuit board including at least a first carrying section (11) and a second section (12), conductor pattern (17a, 17b, 17c) and via holes (14, 14b, 14c), at least one of the sections (11; 12) comprises at least one cavity (13a, 13b) for receiving a least one electric component (15), preferably a naked circuit, the second section (11, 12) constitutes a protective cover essentially hermetical sealing of the component (15). The circuit board (10) comprises substrates of a non ceramic material and that said substrates are protected against moisture penetrating in the transverse direction of the substrates by means scaling arranged at outer edges of the substrates.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: September 10, 2002
    Assignee: Telefonaktiebolaget LM Ericcson (publ)
    Inventor: Mats Söderholm
  • Patent number: 6448507
    Abstract: Damage to and short circuiting of bond fingers on a substrate due to die-attach resin bleed is prevented, thereby increasing yield and improving reliability. Embodiments include forming a trough in a solder mask on a substrate between the bond fingers and semiconductor chip to prevent the die-attach resin from reaching the bond fingers.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edwin Fontecha, Viswanath Valluri, Donald Bottarini
  • Patent number: 6437989
    Abstract: This circuit board contains electronic components having electrical contacts. At least one of the electrical contacts is initially glued to the circuit board using a conductive adhesive and at least one of the electrical contacts is connected to the circuit board by soldering. The circuit board is suitable for fast mechanical mass production. Further a method for the manufacture of the connection between the circuit board and the electronic components is disclosed, in which a solder is applied to soldering points and a conductive adhesive is applied to adhesive points. The circuit board with the components is then placed in a furnace to connect the components to the circuit board.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: August 20, 2002
    Assignee: Endress + Hauser GmbH + Co.
    Inventors: Sergej Lopatin, Dietmar Birgel, Karl-Peter Hauptvogel
  • Patent number: 6418490
    Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: July 9, 2002
    Assignee: International Business Machines Corporation
    Inventor: Jimmy Grant Foster, Sr.
  • Patent number: 6406774
    Abstract: The invention provides an electrically conductive composition for use in a through hole of an electric component, comprising a noble metal powder, a base metal powder and an organic vehicle, the amount of the base metal to 100 parts by weight of the noble metal is about 1 to 95 parts by weight. The composition provides baked electrodes free from structural defects, such as a discontinuity or separation due to shrinkage on calcination.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: June 18, 2002
    Assignee: Murata Manufacturing Co. Ltd.
    Inventors: Shinichiro Banba, Hiroji Tani
  • Patent number: 6395991
    Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert Charles Dockerty, Ronald Maurice Fraga, Ciro Neal Ramirez, Sudipta Kumar Ray, Gordon Jay Robbins
  • Patent number: 6395993
    Abstract: The present invention aims to manufacture a reliable multilayer flexible wiring board at high yield. Flexible wiring board 10 used for multilayer flexible wiring board 40 of the present invention has metal coating 14 on the surface of metal wiring film 19, and metal coating 14 is exposed within the contact region. A wall member rising above the surface of metal coating 14 is provided around the exposed metal coating 14. The wall member is formed of wall face 23 of opening 17 in resin film 15 at the top of metal wiring film 19, for example. When bump 34 having low-melting metal coating 36 is contacted with metal coating 14 in said contact region and heated above the melting point of the solder metal under pressure, low-melting metal coating 36 melts. The molten low-melting metal is stopped by wall face 23 from overflowing outside the contact region so that any bridge cannot be formed by the solder metal between metal wiring film 19.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 28, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Masayuki Nakamura, Mitsuhiro Fukuda
  • Publication number: 20020054484
    Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.
    Type: Application
    Filed: December 4, 1998
    Publication date: May 9, 2002
    Inventors: SALMAN AKRAM, WARREN M. FARNWORTH, ALAN G. WOOD, J. MICHAEL BROOKS, EUGENE H. CLOUD
  • Patent number: 6370030
    Abstract: The present invention relates to a device and a method at a printed board for obtaining good transmission qualities in transmission conductors on a predetermined area (10) of the printed board (11). A separate component (1) for signal transmission comprises a conductor (5). The component (1) is mounted, with the conductor facing the printed board (11), over the area (10) of the printd board, which requires good transmissions qualities, whereby an air gap (L) is obtained between the conductor (5) and the printed board (11). Soldering joints (21) connect each one of the outer parts (7a, 7b) of the conductor (5) of the component (1) to corresponding pattern conductors (17a, 17b) on the printed board (11). The thickness of the soldering connections and the thickness of the pattern conductors form the air gap (L) be the conductor (5) and the printed board (11).
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: April 9, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Roland Bergstedt, Bo Roland Carlberg
  • Patent number: 6365840
    Abstract: The present invention provides an electrical connecting member and an electrical connecting method for achieving electrical connection securely through conductive particles regardless of a slight unevenness of an object matter. An electrical connecting device (10) for electrically connecting an electrical connecting portion (5) of a first object to an electrical connecting portion (3) of a second object comprises an adhesive layer (6) disposed on the first object (4) and constituted of a plurality of conductive particles (7) and a binder (8) containing the plurality of the conductive particles (7) and a paste (9) having a fluidity and disposed on the film-like adhesive layer (6).
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: April 2, 2002
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Noriyuki Honda, Yasuhiro Suga
  • Patent number: 6359233
    Abstract: Disclosed is a printed circuit board multipack, having a plurality of printed circuit boards (for example, a plurality of PCI compliant cards) provided using a common web of substrate material for a printed circuit board. Also disclosed is printed circuit board multipack structure, from which the multipack is formed, and individual printed circuit boards formed from the multipack, and methods of manufacture of each. Printed circuit board structures of the multipack have an internal edge, spaced from the periphery of the web, that is bevelled, and have conductive fingers, e.g., with an electrodeposited gold uppermost layer, extending to the internal edge. The multipack structure includes a common bus bar running adjacent the inner boundary of the printed circuit board structures, and conductive extensions from a conductive base layer of the conductive fingers to the bus bar. Due to the conductive extensions and common bus bar, electrode-position of the gold for the conductive fingers can easily be performed.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: March 19, 2002
    Assignee: Intel Corporation
    Inventors: Steven C. Joy, Michael J. Lane
  • Patent number: 6342682
    Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: January 29, 2002
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoji Mori, Yoichiro Kawamura
  • Patent number: 6340606
    Abstract: The semiconductor device comprises an insulating film in which penetrating holes are formed, a semiconductor chip having electrodes, a wiring pattern adhered by an adhesive over a region including penetrating holes on one side of the insulating film and electrically connected to the electrodes of the semiconductor chip, and external electrodes provided on the wiring pattern through the penetrating holes and projecting from the surface opposite to the surface of the substrate on which the wiring pattern is formed. Part of the adhesive is drawn in to be interposed between the penetrating holes and external electrodes.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: January 22, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6333563
    Abstract: The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by moving the organic interposer using standard rework techniques.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Raymond A. Jackson, Anson J. Call, Mark G. Courtney, Stephen A. DeLaurentis, Mukta S. Farooq, Shaji Farooq, Lewis S. Goldmann, Gregory B. Martin, Sudipta K. Ray
  • Patent number: 6327158
    Abstract: An improved integrated circuit device that includes both bond pads and trim pads is disclosed. Electrically conductive, non-wettable and non-corrosive protective caps are formed over each of the trim pads. With this arrangement, the protective caps act as barriers between the trim pads and solder used to form solder bumps when the IC package is mounted onto a substrate. In one embodiment, the protective caps are formed from a material that is easily sputtered, such as titanium. In a method aspect of the invention, the protective caps are applied during wafer level processing before either the solder bumping or trimming operations.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: December 4, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Nikhil Vishwanath Kelkar, Pai-Hsiang Kao
  • Patent number: 6320139
    Abstract: A bridge structure is utilized on a circuit board. The bridge structure includes a first element, a second element and a gap between the first element and a second element. Soder paste is capable of flowing when the circuit board is heated, such that the paste on the first element comes into contact with paste on the second element. The paste solidifies when cooled such that solidified paste serves to connect the first element and the second element. The first and second elements can be L-shaped.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: November 20, 2001
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Francis R. Byle, Kevin M. McCoy, Todd J. Zorn
  • Patent number: 6316737
    Abstract: In general, in one aspect, the invention features a connection between a through-hole in a circuit board and a contact region on a component. The contact region has a surface bearing a depression. A continuous solder column has one end of that forms a solder joint with an inner wall of the through-hole and the other end of that forms a solder joint with the contact region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: November 13, 2001
    Assignee: VLT Corporation
    Inventors: Michael D. Evans, James D. Goss, Jeffrey A. Curhan, Patrizio Vinciarelli
  • Patent number: 6300576
    Abstract: A printed-circuit board, especially a multilayer printed-circuit board, with projection electrodes integrated with via hole conductors. Each of the projection electrodes is highly adhesive to a corresponding one of the via hole conductors and has high strength, and thus the production method of the printed-circuit board is simplified. Projection electrodes formed of a cured conducting paste are formed in such a manner that the electrodes are integrated with the via hole conductors which consist of a conducting paste embedded into the via hole formed in an insulating resin substrate to form a printed board. The method for producing a printed-circuit board, includes making via holes that penetrate through a prepreg to whose surface a parting film is applied; filling the via hole with a conducting paste; compressing the prepreg under heat to cure the prepreg and the paste; and then peeling off the film.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: October 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Minehiro Itagaki, Hiroaki Takezawa, Yoshihiro Bessho, Tsukasa Shiraishi
  • Patent number: 6297559
    Abstract: A new interconnection scheme of a ball grid array (BGA) module is disclosed where a solder ball is connected to the BGA module by use of an electrically conducting adhesive The electrically conducting adhesive can be a mixture comprising a polymer resin, no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating and others. The solder balls in a BGA module can also be connected to a printed circuit board by use of another electrically conductive adhesive which can be joined at a lower temperature than the first joining to the BGA module. Additionally, an electrically conducting adhesive can be formed into electrically conducting adhesive bumps which interconnect an integrated circuit device to the BGA module.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: October 2, 2001
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Stephen Anthony DeLaurentis, Shaji Farooq, Sung Kwon Kang, Sampath Purushothaman, Kathleen Ann Stalter
  • Patent number: 6259608
    Abstract: A method for controlling the height, shape and placement of solder connections of a surface mount circuit device, such as a flip chip, by way of controlling the extent to which solder is able to flow on a conductor during reflow, but without the conventional use of a solder mask in a manner that results in a portion of the mask remaining beneath the device. Each conductor is defined to include a bond pad and a reduced-width portion adjacent the bond pad. The width of each reduced-width portion is sufficiently narrower than the width of its adjacent bond pad to impede the flow of molten solder onto the reduced-width portion from a solder bump registered with the bond pad. As a result, when reflow soldering a circuit device to the circuit board, molten solder substantially remains on the bond pads and, for a given solder bump size, the bond pads determine the shape and height of the resulting solder connections.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: July 10, 2001
    Assignee: Delphi Technologies, Inc.
    Inventors: Carl Frederick Berardinelli, Thomas M. Otto, Galen J. Reeder
  • Patent number: 6219253
    Abstract: An improved way of preparing packaged electronic circuitry using molded plastics, Thick Film, and Build Up Technology, and achieving shielding of the circuitry and components of the package. In this invention at least one of the electronic devices in the package is supported in a molded pocket in the molded substrate, and using Build Up Technology circuit traces are added to the surface of the substrate and the electronic device, simultaneously creating the circuit traces and making the interconnections with the components at the same time. Shielding, which is optional, can easily be printed or plated over the planar surface of the packaged circuit traces and components.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: April 17, 2001
    Assignee: Elpac (USA), Inc.
    Inventor: William J. Green
  • Patent number: 6215077
    Abstract: A thin-film laminate type conductor is provided which includes a first conductor that is a metal thin film formed of Al or Al alloy, and a second conductor that is a transparent conductive thin film formed of a metal oxide. The first and second conductors are formed in respective patterns on a transparent substrate, such that at least a part of the second conductor is laminated on at least a part of the first conductor. The transparent conductive thin film is composed of an amorphous film. In another embodiment, the first conductor is composed of laminated metal thin films one of which is formed of Al or Al alloy, and the other of which is formed of a high-melting-point metal. The Al or Al-alloy film is sandwiched between the substrate and the high-melting-point metal film.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: April 10, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Makoto Utsumi, Yutaka Terao
  • Patent number: 6198634
    Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: March 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Gregg J. Armezzani, Matthew A. Heller
  • Patent number: 6172879
    Abstract: A method for isolating a pin of a ball grid array (BGA) device mounted on a printed circuit board, and routing the signal carried by the isolated pin to an alternate location. The BGA device pin is isolated by removing the solder ball to expose the device pad. A rework or engineering wire is then soldered to the BGA device pad using a high temperature solder. The rework wire is then routed between the other solder pads to the edge of the BGA device package. The BGA device is then reflowed at a temperature lower than the reflow temperature of the high temperature solder. The rework wire is used to route the signal carried by the isolated BGA pin to an alternate location. The present invention provides for higher process yields than conventional rework processes.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: January 9, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael C. Cilia, Don Nguyen, Gurpreet S. Dayal
  • Patent number: 6163462
    Abstract: A stress relief substrate having a pair of ball grid arrays (BGAs) is interposed between a PC board and an electrical component. The BGAs are electrically connected through vias in the stress relief substrate to connect component circuitry to the PC board. In one embodiment, the BGAs are offset on a flexible substrate so that there is some open space between the edges of electrically connected solder balls. This allows the substrate to warp during thermal cycling and absorb the stress caused by TCE mismatch. In another embodiment, the BGAs are aligned on a rigid substrate that is formed with holes interposed between the solder balls. This reduces the amount of material that interconnects the solder balls so that the substrate tends to flex rather than transfer the TCE stress to the solder balls.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: December 19, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Roy V. Buck
  • Patent number: 6160714
    Abstract: An improved way of preparing packaged electronic circuitry using molded plastics, ceramic Thick Film technology, and Polymer Thick Film technology. In this invention at least one of the electronic devices in the package is supported in a plastic molded substrate, and the circuit traces area added to the surface of the electronic device.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: December 12, 2000
    Assignee: Elpac (USA), Inc.
    Inventor: William J. Green
  • Patent number: 6147311
    Abstract: An anisotropic electro-conductive adhesive layer 14 including an adhesive 15 made of a thermosetting or thermoplastic resin containing electro-conductive particles 16 dispersed therein is formed on a basic circuit board 11 carrying a first circuit pattern 12. A second circuit pattern 18 is formed on the anisotropic electro-conductive adhesive layer 14. An end of the second circuit pattern 18 is curved into the anisotropic electro-conductive adhesive layer 14 to be electrically connected with first circuit pattern 12 via the electro-conductive particles 16. Thereby, the production process can be simplified and the production cost can be reduced. Also, the micro-circuit patterns can be arranged at a high density.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: November 14, 2000
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Mitsutoshi Higashi