With Specific Connection Material Patents (Class 361/779)
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Patent number: 5668700Abstract: There is provided a highly reliable panel assembly structure capable of performing fine-pitch high-density assembling at a high yield and a low cost. A flexible wiring board has a film-like substrate with flexibility, and an IC chip is mounted in an area. In the area is provided a through hole that has plane dimensions smaller than plane dimensions of the chip and penetrates the substrate. Portions that belong respectively to an output side wiring line and an input side wiring line provided on a substrate surface and are connected respectively to an output side electrode and an input side electrode of the chip via second connection materials and are supported by the substrate surface. An output terminal of the flexible wiring board is connected to an electrode terminal formed at a peripheral portion of a panel via a first connection material, while an input terminal of the flexible wiring board is connected to an electrode terminal of a circuit board via a third connection material.Type: GrantFiled: July 24, 1995Date of Patent: September 16, 1997Assignee: Sharp Kabushiki KaishaInventors: Yasunobu Tagusa, Shigeo Nakabu
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Patent number: 5657208Abstract: A hybrid printed circuit board comprising two substrates having different thermal coefficients of expansion can be manufactured using automated surface mount techniques. A daughterboard is configured with a number of contact pads on the bottom. A motherboard is configured with an aligned set of contact pads on the top with solder compound stenciled on them. The daughterboard is attached to the motherboard using standard automated surface mount techniques.Type: GrantFiled: July 28, 1995Date of Patent: August 12, 1997Assignee: Hewlett-Packard CompanyInventors: Terry Noe, Leonard Weber
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Patent number: 5657206Abstract: A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.Type: GrantFiled: January 19, 1995Date of Patent: August 12, 1997Assignee: Cubic Memory, Inc.Inventors: David V. Pedersen, Michael G. Finley, Kenneth M. Sautter
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Patent number: 5650919Abstract: An apparatus, comprising a first member, including two conductive paths, a conductive adhesive, a second member, including two conductive paths, each of the two conductive paths of the second member being connected to a corresponding one of the two conductive paths of the first member via the conductive adhesive, to form two electrical connections, and a peak-shaped dielectric dam, formed on the second member between the two electrical connections.Type: GrantFiled: February 21, 1996Date of Patent: July 22, 1997Assignees: Zymet, Inc., Samsung Display Devices Co., Ltd.Inventors: Karl I. Loh, Chang Hoon Lee
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Patent number: 5650665Abstract: A hybrid IC device has an insulation substrate 1. Circuit patterns 2 made of a thick copper film are formed on the substrate 1. The circuit patterns 2 include terminal patterns 8. Through-holes 7 electrically connect the terminal patterns 8 to terminal patterns 81 formed on the bottom surface of the substrate 1. Active elements such as transistors and ICs and passive elements such as resistors and capacitors are mounted on the top surface of the substrate 1 and are electrically connected to the circuit patterns 2. A conductive pattern 6 made of a thick copper film or a thick silver-platinum film is formed on the bottom surface of the substrate 1. The conductive pattern 6 is used for grounding and heat radiation. The conductive pattern 6 is electrically connected to the active and passive elements via through-holes. The through-holes are usually formed Just under the active and passive elements.Type: GrantFiled: October 23, 1996Date of Patent: July 22, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Tomohiko Yamamoto, Shoichi Tanimata
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Patent number: 5640308Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customized pattern of bonding pads is then formed over the one or both surfaces of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalized pattern of bonding pads may also be formed on the surfaces of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearby via.Type: GrantFiled: November 17, 1995Date of Patent: June 17, 1997Assignee: Aptix CorporationInventors: Robert Osann, Jr., George A. Shaw, Jr., Amr M. Mohsen
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Patent number: 5636104Abstract: A ball grid array package includes a semiconductor chip 4, a circuit board 21 including a plurality of pattern layers of conductive wiring and dielectric layers interposed between the pattern layers which include the first pattern layer 22 and the second pattern layer 23. Electrically conductive wires are provided for interconnecting the semiconductor chip and the conductive wiring, mold resin 4 encapsulates the semiconductor chip and the wiring, and a plurality of solder balls 5 are adhered to a bottom surface of the circuit board 21 and electrically interconnected to the wires via the pattern layers. The surface mounting pad 22 is formed on the first pattern layer and a second conductive pad is formed on the second pattern layer.Type: GrantFiled: August 7, 1995Date of Patent: June 3, 1997Assignee: Samsung Electronics Co., Ltd.Inventor: Sang E. Oh
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Patent number: 5592365Abstract: There is provided a display panel assembly structure capable of achieving a highly reliable connection even when fine-pitch electrode terminals are employed. A second electrode terminal is embedded in a flexible printed circuit board, and protrudes slightly from the flexible printed circuit board within a range of 0 to 2.times.10.sup.-3 mm. By embedding the second electrode terminal in the flexible printed circuit board, an apparent thickness of the second electrode terminal is reduced while keeping the rigidity of the second electrode terminal to thereby improve etching accuracy of a top surface thereof. With the reduction of the protrusion amount of the second electrode terminal, a ratio of a thickness of an anisotropic conductive film to a diameter of a conductive particle can be made to be approximately "1".Type: GrantFiled: December 20, 1994Date of Patent: January 7, 1997Assignee: Sharp Kabushiki KaishaInventors: Takayuki Sugimoto, Yasunobu Tagusa, Hisao Kawaguchi
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Patent number: 5583747Abstract: Conductive thermoplastic interconnects (120) for electronic devices are disclosed. The interconnects may take the form of bumps or spheres, and may be used in applications where metal bumps are conventionally used. Bumps (310) may be attached by retaining them in a vacuum fixture (312) and momentarily contacting them with the substrate (316) requiring the bumps (310). The substrate (316) has been heated sufficiently to cause wetting of the conductive thermoplastic bump (310).Type: GrantFiled: May 5, 1995Date of Patent: December 10, 1996Inventors: John H. Baird, Francis J. Carney
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Patent number: 5576869Abstract: An electrode wiring on a mounting substrate adapted for use in liquid crystal display apparatus, the electrode wiring including portions of Mo or Mo alloy to which bumps of an integrated circuit such as LSI is bonded with conductive paste.Type: GrantFiled: May 3, 1995Date of Patent: November 19, 1996Assignee: Sharp Kabushiki KaishaInventor: Hirokazu Yoshida
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Patent number: 5558928Abstract: A multi-layer circuit panel assembly is formed by laminating circuit panels with interposers incorporating flowable conductive material at interconnect locations and a flowable dielectric materials at locations other than the interconnect locations. Excess materials are captured in reservoirs such as within vias in the circuit panels and apertures in interior elements within the interposers. The flowable materials of the interposers, together with the reservoirs, allow the interposers to compress and take up tolerances in the components. The flowable dielectric material encapsulates conductors on the surfaces of the circuit panels.Type: GrantFiled: July 21, 1994Date of Patent: September 24, 1996Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Scott G. Ehrenberg, Igor Y. Khandros
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Patent number: 5552964Abstract: A switch is provided which is simple in constitution and can be efficiently mounted on a circuit board, and a method of efficiently mounting the switch on the board is also provided. In particular, a switch device comprises a circuit board including a conductor pattern; a fixed contact member provided on a land portion of the conductor pattern; a movable contact member movable to touch/detach with the fixed contact member; a casing for receiving the movable and fixed contact members; locking member for fitting the casing to the circuit board, the locking member being provided in the casing; a holding member for holding the movable contact member with respect to the fixed contact member in one of the touched and detached condition, the holding member being provided in the casing.Type: GrantFiled: November 30, 1992Date of Patent: September 3, 1996Assignee: Kabushiki Kaisha Sankyo Seiki SeisakushoInventor: Hayato Naito
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Patent number: 5542174Abstract: A method for forming solder balls and an apparatus and method for forming solder columns on the electrical contact pads of an electronic package in order to establish a more reliable electrical and mechanical connection between an electronic package and a printed circuit board. In one embodiment, solder balls are formed on the electrical contact pads of a package by placing solder cylinders over the electrical contact pads and then passing the package through a reflow furnace where the solder cylinders take the form of spheres and are wetted onto the pads. In a second embodiment, a laminated solder column is formed that is resistant to collapse during the manufacturing process. The laminated solder column comprises a solder cylinder being clad on its top and bottom surfaces with a solder material having a lower melting temperature than that of the center solder cylinder.Type: GrantFiled: September 15, 1994Date of Patent: August 6, 1996Assignee: Intel CorporationInventor: George W. Chiu
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Patent number: 5541369Abstract: A printed circuit board having juxtaposed thereon in parallel plural conductive paths, at least a part of which has a different length, extending from one end side to the other end side, wherein the electric resistances of the conductive paths are made substantially same by changing the width of at least a part of the conductive paths.Type: GrantFiled: June 5, 1995Date of Patent: July 30, 1996Assignee: Nitto Denko CorporationInventors: Hiroshi Tahara, Seiju Kobayashi, Hitoshi Ohta
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Patent number: 5541814Abstract: A personalizable multi-chip carrier including a substrate, first and second pluralities of conductors arranged on respective first and second parallel planes, the first and second pluralities of conductors defining a grid of conductors arranged over the substrate and defining a multiplicity of crossing locations at which conductors of the first and second pluralities cross each other, apparatus for interconnecting the first and second pluralities of conductors at locations adjacent the multiplicity of crossing locations and including a plurality of fusible links.Type: GrantFiled: October 8, 1993Date of Patent: July 30, 1996Assignee: Quick Technologies Ltd.Inventors: Meir I. Janai, Zvi Orbach
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Patent number: 5506447Abstract: A hybrid integrated circuit of the invention is formed of an insulation substrate, a thick film conductor printed and sintered on the insulation substrate, and a terminal conductor and a circuit part connected to the first thick film conductor. A first electrically conductive metal plate is brazed on the first thick film conductor and connects the circuit part and the first terminal. Electric current between the circuit part and the first terminal mostly flows through the metal plate.Type: GrantFiled: June 7, 1994Date of Patent: April 9, 1996Assignee: Fuji Electric Co., Ltd.Inventor: Tadayoshi Murakami
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Patent number: 5502631Abstract: A new and improved electronic circuit and a method of producing the same is provided in which at least one electronic element is ultrasonically welded to a printed circuit board to create the electronic circuit. Proper alignment between terminals of a conductive circuit pattern on the circuit board and terminal units on the connecting surface of the electronic element is ensured by a variety of techniques: (i) small protuberances on the terminal units, (ii) raised sections on the bottom surface of the terminal units placed to engage indented portions of the board, and (iii) corresponding posts (on the electronic elements) and holes (formed on the circuit board). The ultrasonic welding of the element to the printed circuit board is typically conducted at a frequency range between 25-30 megahertz which produces a vibration which grinds the terminal units of the electronic element to the terminals of the circuit pattern while also welding the element and circuit board together.Type: GrantFiled: October 7, 1994Date of Patent: March 26, 1996Assignee: AUE Institute, Ltd.Inventor: Yoshio Adachi
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Patent number: 5500787Abstract: An electrode wiring on a mounting substrate adapted for use in liquid crystal display apparatus, the electrode wiring including portions of Mo or Mo alloy to which bumps of an integrated circuit such as LSI is bonded with conductive paste.Type: GrantFiled: July 29, 1993Date of Patent: March 19, 1996Assignee: Sharp Kabushiki KaishaInventor: Hirokazu Yoshida
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Patent number: 5490040Abstract: An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.Type: GrantFiled: December 22, 1993Date of Patent: February 6, 1996Assignee: International Business Machines CorporationInventors: Gene J. Gaudenzi, Joseph M. Mosley, Vito J. Tuozzolo, John C. Milliken
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Patent number: 5490042Abstract: A signal line network on a substrate for interconnecting IC chips is programmable after manufacture to define the desired connections. The signal lines comprise line segments arranged end-to-end in both horizontal and vertical directions and are connectible at their ends and the vertical and horizontal segments are connectible at their crossings. A dedicated contact pad is connected to each segment. A plurality of bonding pads are adjacent several segments and each pad has arms extending across the several segments and are individually connectible to them. All connectible junctions comprise amorphous silicon antifuses which are normally insulators and are selectively programmable after the substrate is manufactured by applying a voltage pulse across the antifuse to render it conductive. The pads are arranged in a pattern in cells, all cells having the same pad pattern to facilitate probe connections for programming and testing.Type: GrantFiled: August 10, 1992Date of Patent: February 6, 1996Assignee: Environmental Research Institute of MichiganInventor: Cornelius C. Perkins
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Patent number: 5469333Abstract: An electronic package assembly wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (e.g., printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e.g., polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.Type: GrantFiled: June 1, 1994Date of Patent: November 21, 1995Assignee: International Business Machines CorporationInventors: James V. Ellerson, Richard J. Noreika, Jack A. Varcoe
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Patent number: 5450289Abstract: An arrangement for vertically mounting a semiconductor device to a substrate, e.g., a printed circuit board (PCB), in which a plurality of sequentially arranged external leads of the semiconductor device include at least three different sets of non-consecutive ones of the external leads which have laterally outwardly extending foot portions lying in respective, vertically spaced-apart planes, and in which the foot portions of first and second ones of the sets of non-consecutive external leads are respectively secured to respective first and second steps formed in one of a plurality of walls defining a cavity in the PCB, and a third set of the non-consecutive external leads are secured to a portion of a major surface of the PCB adjacent the cavity.Type: GrantFiled: March 7, 1994Date of Patent: September 12, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Yooung D. Kweon, Min C. An
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Patent number: 5442145Abstract: A terminal for an electric circuit device, comprises a copper core, a gold (Au) layer provided over the copper core, and a nickel (Ni) layer having the thickness of 1.5 .mu.m or less, provided under the gold (Au) layer. In another embodiment, the core is made of an alloy containing (Ni) and covered by a metallized surface layer made of copper.Type: GrantFiled: October 12, 1993Date of Patent: August 15, 1995Assignee: NGK Spark Plug Co., Ltd.Inventors: Ryuji Imai, Toshikatsu Takada
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Patent number: 5420623Abstract: An electricity-heat converter is provided on a substrate for a recording head. The recording head generates heat energy for discharging recording liquid by causing the state change of the liquid to occur. A multi-layer wiring is sandwiched between insulating layers comprising an organic material and is connected electrically to the electricity-heat converter through at least one contact portion formed through the insulating layer. The contact portion is provided in a discharging portion of the recording heads.Type: GrantFiled: August 3, 1993Date of Patent: May 30, 1995Assignee: Canon Kabushiki KaishaInventor: Hideo Tamura
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Patent number: 5417577Abstract: An improved electrical connection between each of a set of metallized areas (16) on a first substrate (11 ) and those on a second substrate (12), via a layer of anisotropically conductive material (22) sandwiched therebetween, is obtained by arraying the metallized areas in concentric rings about each of a plurality of fasteners (28) extending through both substrates and the material. By arraying the metallized areas in concentric rings about each fastener, the anisotropically conductive material in contact with the metallized areas arrayed in each ring will advantageously be subjected to a uniform pressure by the fastener, improving the conductivity of the material.Type: GrantFiled: July 26, 1993Date of Patent: May 23, 1995Assignee: AT&T Corp.Inventors: Albert Holliday, Maureen B. Schmidt, Fred W. Verdi
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Patent number: 5400221Abstract: Electric elements such as a resistance chip, a capacitor chip, a semiconductor device package, and a connector are mounted on a printed circuit board by using at least two methods selected from the re-flow method using cream solder, the chip-on board method using bonding wires, the outer lead bonding method, and the thermal pressing method using heat-seal. The printed circuit board is provided with lands having surface layers of a non-electrolysis Ni--Au plate, a soft Au plate and an electrolysis solder plate, each corresponding to a selected mounting method.Type: GrantFiled: October 21, 1993Date of Patent: March 21, 1995Assignee: NEC CorporationInventor: Joji Kawaguchi
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Patent number: 5383093Abstract: A multilayer substrate is constituted by laminating a plurality of sheet substrates, the respective sheet substrates are constituted by forming conductive layers of a refractory metal such as tungsten (W) on ceramic green sheets composed mainly of an alumina ceramic, and the ceramic green sheets are laminated and sintered to constitute the multilayer substrate. Conductive material layers are formed on the surface of the multilayer substrate so as to be selectively connected to the conductive layers, and copper-plated layers are formed on the conductive material layers. Thick film conductor layers are formed on the copper-plated layers, to constitute terminal conductors, and, a thick film resistor layer for example is connected to the terminal conductors.Type: GrantFiled: July 12, 1993Date of Patent: January 17, 1995Assignee: Nippondenso Co., Ltd.Inventor: Takashi Nagasaka
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Patent number: 5340640Abstract: A printed circuit module, particularly for electronic applications and equipment, comprising a rigid or flexible circuit carrier substrate (1), conductive traces (2) printed on the substrate, and electronic components (5) for electrical connection thereto. The conductive traces comprise a printed ink layer having fine conductive particles embedded therein. The ink is rendered conductive by a touch-contact distribution of the particles in the printed ink layer. The conductive particles comprise electrically conductive crystallites (8) composed of a non-oxidizable crystalline compound of an element of sub-group IV of the Periodic Table, along with nitrogen or carbon. The electronic components (5) are electrically connected to the conductive traces (2) with an anisotropic adhesive (7). The adhesive may also contain the crystallites to effect an electrical connection between the conductive traces (2 ) and the contact areas (6 ) of electronic components (5 ) .Type: GrantFiled: March 24, 1993Date of Patent: August 23, 1994Assignee: Molex IncorporatedInventor: Alfred Bientz
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Patent number: 5328087Abstract: The present invention discloses a thermally and electrically conductive adhesive material comprising a hardened adhesive, and a non-solidified filler containing a liquid metal dispersed in separate spaced regions of the adhesive. The hardened adhesive provides a mechanical bond whereas the filler provides continuous thermal and electrical metal bridges, each bridge extending through the adhesive and contacting the bonded surfaces. The method includes (a) dispersing a filler containing a liquid metal into an unhardened adhesive, (b) contacting the unhardened adhesive and the filler in non-solidified state to the surfaces resulting in separate spaced regions of the non-solidified filler contacting both surfaces, and (c) hardening the adhesive.Type: GrantFiled: March 29, 1993Date of Patent: July 12, 1994Assignee: Microelectronics and Computer Technology CorporationInventors: Richard D. Nelson, Thomas P. Dolbear, Robert W. Froehlich
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Patent number: 5319522Abstract: A method is provided for encapsulating an object with a heat-shrinkable material prior to subjecting the encapsulated object to insert, injection molding. The encapsulation protects the object from thermal damage by preventing contact with the injected polymer. In addition, the encapsulation protects the object from contact by any liquids or other foreign materials which penetrate the molded enclosure.Type: GrantFiled: December 17, 1992Date of Patent: June 7, 1994Assignee: Ford Motor CompanyInventor: Rajendra M. Mehta
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Patent number: 5280139Abstract: A selectively releasing runner and substrate assembly 10 comprises a plurality of conductive runners 16 adhered to a substrate 12, a portion 18 of at least some of the conductive runners 16 have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress.Type: GrantFiled: August 17, 1992Date of Patent: January 18, 1994Assignee: Motorola, Inc.Inventors: Anthony B. Suppelsa, William B. Mullen, III, Glenn F. Urbish
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Patent number: 5266746Abstract: A flexible circuit board including a flexible substrate having an insulating polyimide sheet and a wiring pattern portion formed in a mounting portion and a wiring pattern portion formed in a connecting portion, and a metal substrate on which only the mounting portion of the flexible substrate is secured by means of a thermoplastic polyimide film. Electronic devices are mounted on the mounting portion of the flexible substrate and heat generated by the electric devices can be effectively dissipated through the metal substrate. The connecting portion of the flexible substrate can be connected to an external circuit by means of a connector provided at an edge of the connecting portion. Since the connecting portion is not secured to the metal substrate, connector pins having a large mechanical strength can be used and the connecting portion can be bent at will.Type: GrantFiled: November 27, 1991Date of Patent: November 30, 1993Assignee: Mitsui Toatsu Chemicals, Inc.Inventors: Kunio Nishihara, Yoichi Hosono, Takayuki Ishikawa
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Patent number: 5258577Abstract: An electronic device is made by a method of connecting a circuit member to a substrate. The circuit member is of the type having a discontinuous passivating layer thereon with recesses therein establishing electrical contacts. The circuit member is connected to a mounting surface of a substrate having conductive paths. An adhesive including a resin with spaced conductive metal particles suspended therein is applied over the conductive paths. The distance between the electrical contacts and conductive paths is decreased to provide electrical conduction through the adhesive, while maintaining the adhesive between conductive paths non-conductive. The conductive paths may have established thereon raised or protruding contact surfaces over a portion thereof. The circuit member is mounted on the adhesive while vertically aligning the electrical contacts over pre-selected protruding contact surfaces.Type: GrantFiled: November 22, 1991Date of Patent: November 2, 1993Inventor: James R. Clements