Abstract: There is provided a wired circuit board assembly that prevents breakage of the flexing portion of a wired circuit board supported by a support frame. In a wired circuit board support sheet, a plurality of wired circuit boards include a base insulating layer, a conductor pattern, and a cover insulating layer which are formed on a support board are supported by a support frame in such a manner that they are arranged and aligned in mutually spaced relation. Each of the wired circuit boards has a flexing portion formed by removing the support board to obtain a flexing property. In addition, second connecting portions are provided in spanning relation between the flexing portion and the vertical frame parts of the support frame.

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A printed circuit board with thin film switches for a keyboard including an upper board having multiple circuit lines, an insulating separation defining multiple through holes, a lower board having multiple circuit lines and multiple thin film switches mounted on the upper and lower boards. The thin film switch has two thin film conductive elements respectively formed on the upper and lower boards and correspond to one of the through holes in the insulating separation. Each thin film conductive element has a center conductor, at least two outer conductors formed adjacent to the center conductor, and at least two conductive lines connected to the center and outer conductors. With such an arrangement, the areas of the center and outer conductors will be reduced, surfaces of the conductors are even in the curing procedure of fabricating upper or lower board to keep a stable touching sensitivity.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: A circuit substrate comprises a lamination of plural resin insulation films and includes, on a surface and in an interior of the circuit substrate, plural interconnection layers. One of the plural resin insulation films is formed on a first conductor pattern constituting one of the plural interconnection layers in such a manner that a bottom principal surface of the resin insulation film makes a contact with a surface of the first conductor pattern, the resin insulation film including an opening defined by a sloped surface and exposing the first conductor pattern at the bottom principal surface. A ceramic high-K dielectric film is formed at a bottom of the opening in contact with the surface of the first conductor pattern, wherein there is formed a second conductor pattern constituting one of the plural interconnection layers on the resin insulation film so as to cover the sloped surface and in contact with a surface of the ceramic high-K dielectric film.

Abstract: A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract: A multi-layer circuit board includes a first layer having at least first and second conductive traces of different widths and the same impedance. One of a first power plane and first ground plane has a void region such that the first conductive trace is spaced apart from the first power plane by a first thickness, and the second conductive trace is spaced apart from the first ground plane by a second, different thickness.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.

Abstract: A connecting member between wiring films is provided in which: a normal copper foil, which is a general-purpose component and not expensive, or the like can be used as a material; formation of bumps is sufficiently achieved by conducting etching one time; and a necessary number of layers can be laminated and pressed collectively at a time. Bumps, which are formed approximately in a cone-shape, for connecting wiring films of a multilayer wiring substrate are embedded in a second resin film that serves as an interlayer insulating film.

Abstract: The embodiments of the present invention relate to an improved printed circuit board having additional rows of ground vias to reduce crosstalk in the board. A printed circuit board according to one embodiment of the present invention comprises a first row of vias and a second row of vias, each having a plurality of signal vias. The circuit board also comprises a plurality of rows of vias being coupled to a ground plane between the first row of signal vias and the second row of signal vias. According to one embodiment, the plurality of rows of vias being coupled to a ground plane comprise rows of vias having different sizes. Some of the vias are designed to receive a component, while others are generally smaller and designed to provide a return current path for the signal vias.

Abstract: A circuit board has, in a first signal layer, a signal conductor having a relatively small width and a contact pad having a relatively large width. The relatively large width of the contact pad combined with the relatively narrow signal conductor creates an impedance mismatch between the contact pad and the signal conductor. The circuit board has, in a second signal layer, a ground plane separated from the first signal layer by a nonconductive layer. The circuit board defines an opening in the second signal layer underneath the contact pad. The presence of the ground plane underneath the contact pad typically affects the impedance of the contact pad. The opening in the second signal layer removes a portion the ground plane relative to the contact pad and, therefore, reduces the impedance mismatch between the contact pad and the signal conductor.

Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition with the extreme tip of the tail lying above the bottom of the hole, and the soldering composition is heated to solder the tail to the hole plating.

Abstract: A circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.

Abstract: In recent years, ceramic laminated devices are becoming a focus of great attention as considerable contribution to the miniaturization of high frequency wireless equipment such as a cellular phone, but it is difficult for the conventional ceramic laminated device to secure reliability while maintaining favorable high frequency characteristics. The present invention provides a ceramic laminated device including a reinforcement electrode, which is formed inside a laminated body in which a plurality of ceramic layers, a plurality of inner electrodes and inter-layer via holes are stacked, not electrically connected with inner electrodes nor inter-layer via holes but mechanically connected with the ceramic layers.

Abstract: A multi-layer printed circuit board having a low noise characteristic, the multi-layer printed circuit board includes: at least one circuit layer; at least one isolation line for dividing the at least one circuit layer into at least two areas, the at least one isolation line forms an open pattern and the at least one isolation line extendedly forms a long neck line into the at least one area, and an internal opening of the long neck line located at a geometric center of the at least one area to improve the isolation, especially for the noises near the resonant frequencies of the isolation areas.

Abstract: A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.

Abstract: The present invention provides a method of manufacturing a printed circuit board, which includes preparing a dielectric substrate, coating surfaces of the dielectric substrate, filling a via hole with a conductor, peeling mold-releasing films, compressing the dielectric substrate and forming metal foils. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity.

Abstract: The present invention realizes strengthening of a ground of a lower-surface ground electrode of an upper semiconductor chip and miniaturization in a semiconductor module on which two semiconductor chips are mounted in a stacked manner. A lower semiconductor chip is fixed to a bottom of a recess formed in an upper surface of a module board, and an upper semiconductor chip is fixed to an upper surface of a support body made of conductor which is formed over the upper surface of the module board around the recess. External electrode terminals and a heat radiation pad are formed over a lower surface of the module board.

Abstract: The present invention comprises a plurality of laminating double-side circuit boards and a plurality sheets of prepreg for interlayer connection that are placed one on another. Via holes extend from the circuit on one side of each laminating double-side circuit board to the circuit on the other side thereof. Each via hole is filled with electro-conductive material to connect the circuits on both sides of the laminating double-side circuit board. The pad on a laminating double-side circuit board and the pad on another laminating double-side circuit board are laminated via a sheet of prepreg for interlayer connection so that the respective pads are opposed to each other via the through hole filled with electro-conductive material formed through the sheet of prepreg for interlayer connection. Thereby, the respective pads on the laminating double-side wiring circuit boards are electrically connected with one another.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus.

Abstract: An electronic control unit having a flexible circuit board assembly is disclosed. The electronic control unit comprises a flexible circuit board with at least one layer having first and second portions separated by a bendable region. The electronic control unit further comprises a substantially rigid substrate having first and second portions separated by a bend region and inside and outside surfaces. The first and second portions of the circuit board are affixed to respective first and second portions of the substrate. The bend region has one of the group of a recess and aperture extending outwardly from the inside surface of the substrate with the one of the group of the recess and aperture sized to accept the bendable region of the circuit board.

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: A method for preparing a non-thermal plasma reactor substrate includes disposing electrical vias on green stage first and second ceramic plates; filling the electrical vias with conductive material; and forming electrical contact via cover pads; disposing conductive material on the first ceramic plate to form an electrode plate having a main electrode portion and a terminal lead for electrically connecting the main electrode portion to the electrical vias; laminating the electrode plate and the second ceramic plate together, embedding the electrode therebetween; co-firing the plates to form a laminated co-fired embedded-conductor element; stacking a plurality of the laminated co-fired embedded-conductor elements to form a multi-cell stack, the filled electrical vias aligning in the stack to provide an electrical bus for connecting alternating elements in the stack; and disposing spacers with matching vias and via cover pads between adjacent pairs of elements to form exhaust gas passages.

Abstract: An electronic circuit board having an optical wiring layer sandwiched between two electrical wiring layers. The optical wiring layer is structured to be a two-dimensional optical waveguide. An E/O device and an O/E device are provided in the optical wiring layer or at an interface between the optical wiring layer and the electrical wiring layer. A via piercing the optical wiring layer connects the two electrical wiring layers. It is possible to efficiently input and output light to and from an optical wiring layer.

Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.

Abstract: In a laminated ceramic electronic component, the sectional size of via-hole conductors extending through thicker ceramic layers is larger than that of via-hole conductors extending through thinner ceramic layers. This makes it possible to facilitate filling of a conductive paste for the via-hole conductors having a larger height and to inhibit a conductive paste for the via-hole conductors having a smaller height from being lost after filling.

Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated in a first layer (31) that will become the topmost layer of the stack, to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition, and the soldering composition is heated to solder the tail to the hole plating.

Abstract: Power and ground planes that are used in Printed Circuit Boards (PCBs) and that comprise porous, conductive materials are disclosed. Using porous power and ground plane materials in PCBs allows liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

Abstract: An interconnect for use with a pixel layer of a pixel web is provided, the interconnect including an interconnect substrate having a plurality of conductive leads and a plurality of contact vias formed on and extending from the interconnect substrate. The contact vias are formed in a predetermined pattern on the interconnect substrate and are in electrical communication with the conductive leads. The interconnect includes a patterned spacer of a thickness substantially equal to a height of the contact vias. The patterned spacer includes a plurality of through-holes also formed according to the predetermined pattern and having a dimension substantially equal to a dimension of the contact vias. The interconnect substrate and the patterned spacer are capable of being assembled onto the pixel layer, with the patterned spacer being in a middle position and the contact vias extending through the through-holes to contact corresponding cathode portions on the pixel layer.

Abstract: A printed circuit board having a permanent solder mask includes a substrate made of a glassfiber reinforced epoxy resin material. The top and bottom surfaces of the substrate are disposed thereon a conductive pattern respectively. An epoxy resin solder mask is coated on each surface of the substrate in such a way that the conductive pattern is divided into a sheltered portion covered by the solder mask and an unsheltered portion exposed outside. The solder mask also has an even and smooth outer surface with a micro-roughness ranging between 0.5 ?m˜10 ?m and an optimum thickness ranging between 2 ?m˜200 ?m.

Abstract: Signal wiring conductors are provided at opposing positions on the upper surface of the uppermost dielectric layer and on the lower surface of the bottommost dielectric layer, and grounding conductors surrounding grounding-conductor non-forming areas are provided on the upper surfaces of intermediate dielectric layers and the bottommost dielectric layer. These grounding conductors form an electromagnetically shielded space by being connected by grounding-conductor via conductors vertically penetrating the respective dielectric layers around the grounding-conductor non-forming areas, and signal via conductors are so provided in the respective dielectric layers as to penetrate this electromagnetically shielded space.

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Abstract: A wiring board with microstrip structure has: a first conductor layer that is provided with conductor wirings to be connected to a semiconductor chip in its external terminal (bonding pad); a second conductor layer that is provided with a conductor pattern connected through a via to a ground wiring, for supplying a power supply of ground potential to the semiconductor chip; and a third conductor layer that is provided with a power supply terminal connected through a via to a power supply wiring for supplying an operation power supply of a potential other than the ground potential to the semiconductor chip, a signal terminal connected through a via to a signal wiring for transmitting an electric signal, and a ground terminal connected through a via to the conductor pattern in the second conductor layer.

Abstract: In order to provide a wiring board comprising a magnetic material effective in suppressing spurious radiation in semiconductor devices and electronic circuits and the like that operate at high speeds, a wiring board (15) comprises an insulative base material (17), conductor patterns (19a to 19f) formed thereon, and magnetic thin films (21a to 21f) formed on the conductor patterns (19a to 19f).

Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A monolithic ceramic substrate includes a green laminate having a plurality of green functional ceramic layers including a functional ceramic material, green support layers including a ceramic material that does not sinter at a sintering temperature for the green functional ceramic material to prevent shrinkage of the functional ceramic layers, first conductor patterns including a thin-film conductor, and second conductor patterns including a thick-film conductor. The green laminate is fired at the sintering temperature for the green functional ceramic material.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: The power part and the logic part of the module are arranged on different substrates. The circuit board (5) of the logic part has a recess (6) in which the power substrate (2) is located and electrically connected to the logic part by wire bonding techniques (7).

Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: An outer coating substrate for an electronic component is constructed to be calcined at a low temperature, and greatly decreases the cost thereof while greatly improving the dimensional precision of the substrate. The outer coating substrate for an electronic component includes a multi-layered substrate including a first material layer that is sintered in a liquid phase and a second material layer that is not sintered at the sintering temperature of the first material layer. The first and second material layers are laminated, and calcined at the calcining temperature of the first material layer.

Abstract: A resistor-capacitor network for terminating transmission lines. The network includes a core of dielectric material. Capacitors are formed within the core from spaced apart electrode plates. Terminals extend from the electrode plates to a top surface of the core. The electrode plates are oriented perpendicular to the top surface. Ball pads are located on the top surface. Resistors are located on the top surface and are connected between the ball pads and terminals. Conductive spheres are attached to the ball pads.

Abstract: A multi-layer circuit board having apertures that are selectively and electrically isolated from electrically grounded member and further having selectively formed air bridges and/or crossover members which are structurally supported by a polymeric material. Each of the apertures selectively receives an electrically conductive material.

Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.