Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract: An electronic device includes: a substrate; a plurality of operating elements provided in an operating region of the substrate; a first wiring pattern which is provided outside the operating region in the substrate so that the first wiring pattern has the width longer than the operating region; a first electrode formed in a layer different from the first wiring pattern, partially overlapping the first wiring pattern, and supplying common electrical energy to the operating elements; and a conductive section provided in a region in which the first wiring pattern partially overlaps the first electrode, electrically connecting the first wiring pattern to the first electrode.

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

Abstract: A flexible rigid printed wiring board includes a plurality of rigid wiring boards having wiring patterns. The rigid wiring boards are spatially separate from each other. The flexible rigid printed wiring board also includes a flexible portion. The flexible portion connects the rigid wiring boards, and includes an insulating and flexible resin sheet. The insulating and flexible resin sheet includes first portions of first and second sub resin sheets. The first portions of the first and second sub resin sheets are bonded together. The first and second sub resin sheets have second portions covering and adhering to surfaces of the rigid wiring boards.

Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.

Abstract: A packaging structure of a driving circuit for a liquid crystal display device includes a base film, a plurality of first metal lines formed on the base film and arranged to have a certain distance between neighboring first metal lines, an insulating film on the first metal lines, wherein the insulating film exposes both ends of the first metal lines, a plurality of second metal lines on the insulating film, wherein the second metal lines are formed parallel to the first metal lines and an overcoat layer on the second metal lines and exposing ends of the first and second metal lines.

Abstract: A molded interconnect device (MID) having a multilayer circuit of a reduced thickness, in which a layer-to-layer connection(s) is formed with high reliability, is provided as a multilayer circuit board. The multilayer circuit board comprises a substrate having a first surface and a second surface extending from an end of the first surface at a required angle relative to the first surface, and the multilayer circuit formed on the first surface and composed of a plurality of circuit layers. Each of the circuit layers is provided with a conductive layer having a required circuit pattern and an insulation layer formed on the conductive layer by film formation. The layer-to-layer connection of the multilayer circuit is made through a second conductive layer formed on the second surface of the substrate.

Abstract: A connector pad includes projections extending radially outwardly from an inner portion of the pad to help stabilize and reinforce the pad. The added stability allows the radial thickness of an inner portion of the pad to be reduced. This decreases the surface area of the pad and reduces the opportunity for capacitive build up to occur relative to an associated conductive plane in a circuit board.

Abstract: A high-speed router backplane is disclosed. Because of the large number of high-speed conductive traces present in such a backplane, electromagnetic interference (EMI) can be a serious issue. And because such a router consumes significant amounts of power, some provision must exist (e.g., bus bars in the prior art) within the router for distributing power to the router components. In preferred embodiments, power distribution is accomplished using relatively thick (e.g., three- or four-ounce copper) power distribution planes within the same backplane used for high-speed signaling. To shield these planes from EMI, they are preferably placed near the center of the material stack, shielded from the signaling layers by adjacent digital ground planes. Also, where two power supply planes exist, the power supply planes are placed adjacent, further shielded by their respective power return planes.

Abstract: There is disclosed a method of producing a ceramic multilayer substrate by laminating a plurality of glass-ceramic green sheets made of a glass-ceramic containing an organic binder and a plasticizer to form a laminate; and firing the laminate; further comprising: applying to or overlaying on the surfaces of the glass-ceramic green sheets inorganic compositions, the sintering temperature of the inorganic compositions being higher than that of the glass-ceramic green sheets; laminating a plurality of the glass-ceramic green sheets having the inorganic compositions applied to or overlaid on the surfaces of the glass-ceramic green sheets respectively, to form a part of the laminate; and laminating a plurality of the glass-ceramic green sheets to form the other part of the laminate.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: In holes formed in a multi-layer wiring board for transmitting differential signals, a first hole is formed, an insulating portion is formed by filling the first hole with an insulating resin, a pair of second holes is formed for transmitting the differential signals to the formed insulating portion, and the pair of second holes is arranged symmetrically each other with respect to a center axis of the first hole for forming a coaxial structure.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

Abstract: A packaged die (112) for an integrated circuit (62) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit (62) is still in a wafer format. A wafer substrate (64) on which the integrated circuits (62) have been fabricated is patterned and etched to form signal and ground vias (74, 72) through the substrate (64). A back-side ground plane (82) is deposited in contact with the ground vias (72). A protective layer (90) is formed on the top surface (76) of the substrate (64), and a protective layer (98) is formed on the bottom surface (84) of the substrate (64), where the bottom protective layer (98) fills in removed substrate material between the integrated circuits (62). Vias (106) are formed through the bottom protective layer (98), and the wafer substrate (64) is diced between the integrated circuits (62).

Abstract: A multilayer circuit board that has electrodes only on one surface is manufactured as follows. A plurality of conductor layers are formed on a resin film made of thermoplastic resin to form a single-sided conductor layer film. Then, a plurality of via-holes 24, which are bottomed by the conductor layers, are formed in the resin film. Then interlayer connecting material is packed in the via-holes 24 to form a single-sided conductor layer film having the interlayer connecting material. A plurality of single-sided conductor layer films are formed and stacked such that surfaces having the conductor layers face in the same direction. Then, the single-sided conductor layer films are pressed and heated to complete the multilayer circuit board. The multilayer circuit board is formed by using only the single-sided conductor layer films and pressing once, so the manufacturing process is simplified.

Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: A multilayer wiring board comprising a plurality of conductor patterns stacked with an insulating layer composed of a thermosetting resin interposed between adjacent conductor patterns, wherein the insulating layers are each formed of a pair of film-like thermosetting resin layers and a resin film having a lower coefficient of linear expansion than, and sandwiched between, the thermosetting resin layers, and wherein the electrical connection between the stacked conductor patterns is established by vias formed through the insulating layers. A method of fabricating such a multilayer wiring board is also disclosed.

Abstract: In an electronic circuit equipment using a multilayer circuit board on which a semiconductor chip is mounted, a thin film capacitor is provided on the multilayer circuit board. Moreover, a first electrode of the thin film capacitor and a first wiring of the multilayer circuit board are electrically connected to each other, and a second electrode of the thin film capacitor and a second wiring of the multilayer circuit board are electrically connected to each other, respectively. Furthermore, a thin film dielectric of the thin film capacitor was grown epitaxially with the first electrode as its base. The employment of the multilayer circuit board makes it possible to provide the electronic circuit equipment using the multilayer circuit board that includes the built-in thin film capacitor having the high dielectric-constant thin film dielectric.

Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A multi-layer laminate on which electrical devices may be mounted includes a printed circuit portion, a first electrically isolating layer and a substantially rigid base. The printed circuit portion has a first major surface to receive one or more electrical devices to be mounted on the multi-layer laminate, and further has an electrically conductive layer having one or more conductive traces to be electrically connected to one or more of the electrical devices to be mounted on the multi-layer laminate. The laminate further includes at least one adhesive layer comprising an adhesive that is activatable at a first set of processing conditions, and re-activatable at a second set of processing conditions.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads while the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads isn't electrically connected with anyone of the first pads, and other second pads that located adjacent to this second pad, which is not electrically connected with the first pads, electrically connect to the interconnection-wiring layer. Furthermore, this invention also discloses a semiconductor device including the substrate.

Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.

Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A multilayered circuit board according to the present invention includes at least first and second stacked insulating layers. The first insulating layer has thereon a first electric conductor made of a conductive film constituting an inductor and a first electrode made of a conductive film constituting a capacitor. The second insulating layer has thereon a second electrode made of a conductive film constituting a capacitor. The first and second insulating layers are stacked such that the first and second electrodes are opposed to each other through the insulating layers. Therefore this provides a circuit board having a capacitor and an inductor through the use of the two insulating layers, thus providing an inexpensive thin circuit board with small parts count and high work-efficiency compared with the use of three insulating layers in a related art.

Abstract: A voltage controlled oscillator is provided. The oscillator includes a surface acoustic wave element for forming a feedback circuit for an amplifier, and a phase adjustment circuit including a filter which is interposed in the feedback circuit. The oscillator also has a phase shifter including a hybrid coupler to which an additional control part is attached for changing a phase value within an oscillation loop with a control voltage supplied from an external source. An equal power divider equally distributes output power within the oscillation loop and supplies the output power outside the oscillation loop. A multi-layer board is used for mounting the amplifier, surface acoustic wave element, phase adjustment circuit, phase shifter, and equal power divider in at least two separate layers.

Abstract: Electrical connections are made between a pair of elements disposed on opposite side of the hole extending through a dielectric layer by evaporating a conductive material such as a metal having high vapor pressure within the hole while maintaining the hole in a substantially sealed condition. The process may be performed simultaneously to form numerous connections within a microelectronic unit as, for example, within a multilayer circuit panel.

Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.

Abstract: A high frequency module device of a thin type, high precision and high functions in which the size and the cost of the package may be diminished. The module device includes a base substrate (2) and a high frequency device layer (4). The base substrate (2) is formed by forming a patterned wiring layer (9) on a first major surface (5a) of a core substrate (5) molded of an organic material exhibiting thermal resistance and high frequency characteristics. The uppermost layer of the base substrate (2) is planarized to form a high frequency device layer forming surface (3). The high frequency device layer portion (4) is formed on the high frequency device layer forming surface (3) by a thin film or thick film forming technique and includes intra-layer passive elements, made up of a resistor (27) and a capacitor (26). The passive elements are supplied with power or signals from the side base substrate.

Abstract: A multi-layered circuitized substrate for high-frequency applications. Conductive via-holes extend between two non-adjacent conductive layers for transmitting high-frequency signals therebetween. For each via-hole, shielding rings connectable to a reference voltage are provided, each ring formed in a corresponding intermediate conductive layer between the two non-adjacent conductive layers. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands at the ends thereof, in order to reduce stray capacitance associated with the via-hole without losing the shielding effect provided by the rings.

Abstract: A low temperature co-fired ceramic assembly (LTCC) with a constraining core of differing dielectric constants that minimizes shrinkage of the outer ceramic layers during firing. The ceramic assembly has a planar ceramic core. The core has a first ceramic layer with a first dielectric constant and a second ceramic layer adjacent to the first ceramic layer. The second ceramic layer has a second dielectric constant. A third ceramic layer has a third dielectric constant. A fourth ceramic layer has a fourth dielectric constant. The ceramic core is located between the third and the fourth ceramic layers. Several electrically conductive vias extend through the first, second, third and fourth ceramic layers. Several circuit features are located on the first, second, third and fourth ceramic layers. The vias electrically connect the circuit features on the layers.

Abstract: A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.

Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.

Abstract: The covering sheet includes at least one magnetic material layer made of a resin compound having an oxide magnetic material or a metal magnetic material mixed therein, a ground conductor layer laminated on one surface of the magnetic material layer, and a plurality of via holes for passing conducting unit for grounding the ground conductor layer, or includes a laminate consisting of at least one magnetic material layer made of a resin compound having an oxide magnetic material or a metal magnetic material mixed therein and at least one dielectric layer having a permittivity lower than that of the magnetic material layer, and a ground conductor layer laminated on one surface of the laminate.

Abstract: A semiconductor device package and method of fabricating the same. The semiconductor device package includes The package may include a variety of semiconductor dice thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements are also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

Abstract: There has been a problem that a mode (a high-order mode) different from a basic propagation mode occurs at a point of a through conductor and a transmission characteristic deteriorates greatly. The present invention is a high-frequency wiring board wherein L>&lgr;/4 and &pgr;(A+B)≦&lgr; are satisfied in which L is a length of a through conductor, A is a diameter of the through conductor, B is shortest distances between the through conductor and a plurality of ground through conductors, &pgr; is a circle ratio and &lgr; is an effective wavelength of a high-frequency signal transmitted by the through conductor. It is possible to inhibit a high-order mode which occurs at a point of the through conductor.

Abstract: A circuit board having stable connection resistance can be obtained . The multi-layer circuit board includes the steps of making through-holes in a incompressible substrate having films on either side thereof via a bonding layer; filling conductive paste into the through-holes; removing the films from the substrate; laminating metallic foils to either side of the substrate and heating same under pressures to harden the bonding layer, bonding the metallic foils to the substrate and electrically connecting the sides of the substrate to each other; and forming a circuit pattern by machining the metallic foils.

Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

Abstract: The invention relates to a transponder provided with an integrated circuit, an antenna, and a first capacitor provided with a dielectric and a first and a second capacitor electrode, which transponder comprises a stack of layers, i.e.: a first layer of a dielectric material, a first patterned electrically conductive layer of which the antenna forms part, a second layer of a dielectric material, and a second patterned electrically conductive layer. The invention further relates to an appliance provided with a transponder which comprises an integrated circuit, an antenna, and a first capacitor.

Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.

Abstract: A laminated ceramic electronic component includes an embedded portion formed in the periphery of an external terminal electrode so as to extend and be embedded in a component main member defined by ceramic layers, whereby affects of a small edge angle are eliminated.