Abstract: A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and an n-type carbon nanotube thin film transistor stacked on one another. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: An active matrix light emitting diodes display module integrated with single-walled carbon nanotubes control circuits includes a light emitting diode pixel having a crystalline semiconductor light emitting diode, single-walled carbon nanotubes switching transistors and a charge storage capacitor.

Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A cable exit trough is mountable to a lateral trough section either during initial assembly of the cable routing system, or at a later date. The exit trough includes a bracket portion mountable to the top edge of one of the sides of the lateral trough section. Two lead-ins are provided to lead the cable in an upward direction from the lateral trough section to the exit trough. The exit trough includes an exit trough portion extending from the bracket portion upwardly away from the lateral trough section. The exit trough portion includes a convexly curved bottom trough surface, and two convexly curved upstanding sides. The exit trough portion and the lead-ins define a cable pathway from the lateral trough section to an exit point of the exit trough portion which can either lead downwardly relative to the lateral trough section or horizontally.

Abstract: A nanotube random access memory (NRAM) structure is provided. The structure includes a substrate, a gate electrode disposed in the substrate, and a first nanotube fabric disposed on the substrate. The first nanotube fabric has a channel region spaced apart from the gate electrode by a portion of the substrate. The structure also includes a drain contact contacting the first nanotube fabric. The structure also includes a second nanotube fabric disposed on the substrate, and is adjacent and connected to the first nanotube fabric. The structure also includes a source contact contacting the second nanotube fabric. The first nanotube fabric is a high-voltage fabric compared to the second nanotube fabric such that when a voltage is applied across the first nanotube fabric and the second nanotube fabric via the drain contact and the source contact, the second nanotube fabric is permitted to switch without switching the first nanotube fabric.

Abstract: Three-trace electromechanical devices and methods of using same are described. The device of the present invention includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. The nanotube ribbon is capable of maintaining its position after removing an electrical stimulus applied to at least one of the first and second electrically conductive elements. Such devices may be formed into arrays of cells. One of the conductive elements may be used to create an attractive force to cause the nanotube ribbon to contact a conductive element, and the other conductive element may be used to create an attractive force to pull the nanotube ribbon from contact with the contacted conductive element. The electrically conductive traces may be aligned or unaligned with one another.

Abstract: A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.