Abstract: Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.

Abstract: A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

Abstract: A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.

Abstract: Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array substantially similar or identical to a portion of a ferroelectric data array is precharged and then coupled with a bitline in the data array to provide a reference voltage according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.

Abstract: A memory cell system for a dynamic random access memory (DRAM) array is disclosed. In an exemplary embodiment of the invention, the system includes a plurality of data storage elements arranged in rows and columns. A plurality of wordlines corresponds to the columns, and a plurality of lower bit lines corresponds to the rows, with each of the plurality of lower bitlines further being associated with a plurality of upper, complementary bitlines thereto. The plurality of upper bitlines are vertically aligned with the plurality of lower bitlines, thereby defining a plurality of vertically folded bitline pairs. Further, a plurality of sense amplifiers are arranged in the rows, with each of said plurality of sense amplifiers having one of said plurality of vertically folded bitline pairs as inputs thereto. When one of the plurality of wordlines is activated, a subset of the rows corresponding to the vertically folded bitline pairs is activated.

Abstract: In a bistable magnetic element, a pulse current or a dc-biased high frequency current is supplied to a soft magnetic material which has a helical magnetic anisotropy. As a result, the magnitude of a voltage induced across the soft magnetic material abruptly changes with respect to variation in an external magnetic field.

Abstract: A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled.

Abstract: A device includes a core, such as a wire or cylinder of a solid material such as nonmagnetic metal, coated with a film of a material having a high degree of magnetostriction and a uniaxial helical magnetic anisotropy at an oblique angle to the longitudinal axis of the core. The device has the characteristic of being magnetically bistable and of providing a large magnetic pulse as it changes to one of its stable states in response to passage of a magnetic field by it. To achieve a helical magnetic anisotropy, the magnetostrictive film can be applied to a nonmagnetic wire by plating the wire while it is under torsion, twisting a plated wire after plating, or by applying an electric current and a magnetic field to the wire as the film is being plated or annealed.

Abstract: A threshold magnetic switch is described, with adjustable threshold level for varying applications, or for purposes of matching sensitivities of several switches in utilizing apparatus.