Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by applying a plurality of programming signals having different characteristics to the cell. The programming signals include at least a first programming signal which programs the cell by a first increment and a subsequent programming signal which programs the cell by a second increment smaller than the first increment. As the cell is being programmed to a selected state, its programming status is verified independently of reference values bounding the memory states. For this purpose, a signal indicative of the programming status (e.g., the cell's bit line signal) is compared with a reference signal corresponding to the selected state but having a value different from the reference value or values bounding the selected state. The programming operation can thus be controlled without actually reading the memory state of the cell.

Abstract: The invention provides a method and system for improved CAM match line precharge, in which the amount of power consumed by match line precharge and discharge is significantly reduced. An independent match precharge voltage is introduced to the CAM, which is used to separately precharge the match line and is available for use by comparison circuits to attempt to match the input tag. The match precharge voltage is selected so as to reduce the relative power consumption for match line precharge and discharge by a factor of about five. Optionally, sense amplifiers in the comparison circuits are disposed so as to compare each discharged match line with the match precharge voltage itself.

Abstract: In a region of a transfer gate provided in a central portion of multilevel writing bit lines, noise in adjacent bit lines at the time of re-writing is counteracted by reversing the order of complementary bit line pair every other pair. With this, in a multilevel dynamic type semiconductor memory device in which one sense amplifier commonly includes a plurality of bit lines and some of the bit lines are selectively activated in a time-dividing manner, the influence of noise between the adjacent bit lines can be deleted.

Abstract: A memory system having memory cells for storing one of a plurality of threshold levels to store more than a single bit per cell is disclosed. The memory system contains a switch control to permit selection of an operating mode including a multi-level cell mode and a standard cell mode. The memory system further includes a reading circuit to read a single bit per cell when operating in the standard cell mode, and to read multiple bits of data per memory cell when operating in the multi-level cell mode. A program circuit programs a single bit of data per memory cell for addressed memory cells when operating in the standard cell mode, and programs multiple bits of data per memory cell for addressed memory cells when operating in the multi-level cell mode.

Abstract: A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Abstract: A ferroelectric memory comprises a DA converter for receiving any one of 3 digital values as write data and for applying a write analog voltage corresponding to the input digital value to a electrode of a ferroelectric capacitor in order to cause the residual dielectric polarization in the ferroelectric capacitor, and an AD conversion circuit for receiving a read analog voltage obtained in accordance with the residual dielectric polarization value of the ferroelectric capacitor and for restoring the read analog voltage to the original digital value. In the ferroelectric capacitor, residual dielectric polarization corresponding to the write analog voltage occurs. The value of the residual dielectric polarization can be set to a plurality of values corresponding to the write analog voltage. Therefore, among 3 or more values of the write data, a predetermined value is stored in the ferroelectric capacitor.

Abstract: An apparatus for determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: Disclosed herein is an integrated circuit memory device which includes a memory cell arranged at an intersection of a word line and a bit line and a bit line precharge circuit for providing the bit line with a predetermined current during respective bit line precharge and sensing periods of time of a data reading operation in response to a bit line precharge signal. The integrated circuit memory device further includes a bit line pass transistor which has a gate and connected between the bit line precharge circuit and the bit line and which transfers the current from the bit line precharge circuit onto the bit line. Furthermore, the device includes a bias voltage supplying circuit which supplies the gate of the bit line pass transistor with a bias voltage during the data reading operation.

Abstract: A semiconductor multivalued read only memory device stores multivalued data in a memory cell array and multivalued reference data in reference cell arrays, and stepwise changes word lines and reference word lines to different active levels for reading out the multivalued data and the corresponding multivalued reference data at different timings so as to determine the value of each multivalued datum by comparing it to the multivalued reference data without undesirable influence of deviated threshold and unintentionally deviated active level.

Abstract: A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.

Abstract: A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.

Abstract: A memory device for storing multi-data comprises an input level detector for receiving data through n input terminals and selecting one of 2.sup.n output terminals corresponding to the data inputted to the input terminals; a word line switching unit for outputting one of 2.sup.n reference voltages corresponding to the outputs from the input level detector; and a word line driver for receiving the output from the word line switching unit and transferring it to the corresponding word line of the memory device.

Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

Abstract: An apparatus for controlling reading of memory cells in a memory device includes a word line voltage generator operative to apply a word line voltage to a selected memory cell of memory device responsive to a sensing period signal. A dummy memory cell is coupled to the word line voltage generator such that the word line voltage is applied to the dummy memory cell, the dummy memory cell having a threshold voltage. A sensing period controller is coupled to the dummy memory cell and operative to produce the sensing period signal responsive to a current generated in the dummy memory cell. According to an embodiment of the present invention, the sensing period controller includes a dummy sense amplifier coupled to the dummy memory cell and operative to produce a dummy cell sense amplifier output signal responsive to a current in the dummy memory cell.

Abstract: A multivalue dynamic random access memory cell and method therefor are provided. Sense circuitry for sensing a most significant bit (MSB) and a least significant bit (LSB) of a binary data value are coupled to an unsegmented complementary bitline pair. The binary data is represented by a multilevel voltage stored on a storage element in the DRAM cell. A reference signal is provided to the sense circuitry, wherein the reference signal is independent of a precharge on the bitline pair. Cross-coupling elements offset the reference signal in response to the sensing of the MSB, whereby the voltage levels corresponding to the LSB are sensed. Following a read, the multilevel data value is restored on the storage element by a restore/write unit including a programmable voltage supply. The detected MSB/LSB pair are input to the restore/write unit which outputs the corresponding voltage level to the DRAM cell.

Abstract: A column of read-only-memory (ROM) cells is programmed to store two or more bits of information in each cell by forming a plurality of coding (bit) lines adjacent to the column of cells, and selectively connecting the cells to the plurality of coding lines so that the different logic conditions defined by the two or more bits are represented by the coding lines that are connected to a memory cell.

Abstract: A semiconductor integrated circuit having a standard pair of complementary data lines subjected to ternary control, through which data complementary to each other are transmitted when valid data are transmitted, single data lines subjected to binary control, through which data of the same system as that of the pair of complementary data lines are transmitted and a circuit for detecting valid data in a standard intermediate latch circuit which detects an event that the data transmitted through the standard pair of complementary data lines are changed to data complementary to each other, wherein the circuit for detecting valid data confirms arrival of the valid data and controls data corresponding to the data transmitted through the single data lines, to thereby reduce the number of pairs of data lines for narrowing an wiring area of the data lines and reducing a chip size while maintaining a high speed operation.

Abstract: A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract: A semiconductor dynamic random access memory device has memory cells each storing a piece of multiple-valued data equivalent to two-bit binary data in the form of electric charge, and sub-bit line pairs selectively connected to the memory cells use parasitic capacitors coupled thereto as charge accumulators weighted by two, wherein the piece of multiple-valued data transferred from the sub-bit line pair to a main bit line pair supplies a first potential level to one of the charge accumulators assigned to the most significant bit and a second potential level to another of the charge accumulators assigned to the least significant bit, and dummy cells are selectively coupled to the charge accumulators so as to make storage capacitance coupled to the charge accumulator assigned to the most significant bit twice as large as the storage capacitance coupled to the charge accumulator assigned to the least significant bit, thereby eliminating electrical influence of the storage capacitor of the selected memory cell fr

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

Abstract: A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.

Abstract: A method and apparatus are provided for performing hierarchical address translation by translating each ternary hierarchical address into a binary address and a binary priority mask and storing the binary addresses in the binary CAM. A binary search of the priority masks is then performed by searching the CAM with a priority mask and choosing a next priority mask depending on the results of the search of the CAM until a correct matching entry (i.e., the matching entry with the lowest hierarchical level) is found. This technique only requires log.sub.2 N searches of the CAM, where N is the number of hierarchical levels represented by the priority field. A method and apparatus are also provided for performing hierarchical address translation by storing table entries including a priority field in a ternary CAM and performing only a fixed number of searches of the CAM.

Abstract: A multilevel DRAM sensing structure to detect the level of charge and interpret the digital data from a DRAM cell is disclosed. The multi-level sense amplifier structure has a first and second bit line each having a first and second section. A pair of isolation switch transistors separate the first section of the first bit line from the second section of the first bit line. The first section of the second bit line is separated from the second section of the second bit line by a second pair of isolation switch transistors. A latching sense amplifier has a first input connected to one of the pairs of isolation switch transistors, a second input connected to the other pair of isolation switch transistors, and an output connected to external circuitry. The output will have the digital data represented by the charge in the DRAM cell.

Abstract: An apparatus for determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

Abstract: A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports. A NULL convention register file includes: a NULL convention input register; and a plurality of NULL convention storage registers. The input register synchronously propagates alternating wavefronts of NULL and data to an addressed NULL convention storage register.

Abstract: A method for driving a word line in a multi-value mask ROM comprises the consecutive steps of precharging the word line by a source potential, setting the word line at a first potential which is lower than the source potential and reading data from a selected memory cell, precharging the word line by the source potential, charging the word line at the second potential which is lower than the source potential and reading data from the selected memory cell, setting the word line at the source potential and reading data from the selected memory cell. The precharge of the word line reduces the read time for the multi-value mask ROM.

Abstract: A programmable memory circuit including the facility to reconfigure it's format

Abstract: A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented.

Abstract: The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.

Abstract: A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

Abstract: A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.

Abstract: The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted.

Abstract: A semiconductor memory device includes a multilevel memory cell array having a plurality of multilevel memory cells each storing data of at least three bits, a regular memory cell array having a plurality of regular memory cells each storing data of two bits, a first X decoder which selects a word line of the multilevel memory cell array corresponding to an input address, a second X decoder which selected a word line of the regular memory cell array corresponding to the input address, a pulse generator circuit which generates a plurality of pulse signals with mutually different active periods, a voltage generator circuit which generates a control signal whose voltage varies stepwise corresponding to the levels of the plurality of pulses, supplying circuit for supplying the control signal to the selected word line of the multilevel memory cell array, selecting circuit for selecting a bit line of either one of the regular memory cell array or the multilevel memory cell array in response to the input address and

Abstract: An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs.

Abstract: A memory cell has two magnetoresistive memory elements, each with at least two ferromagnetic layers. The electrical resistance of each memory element differs depending on whether the ferromagnetic layers are magnetized in the parallel or antiparallel state. Binary information is stored in the memory cell by supplying currents that generate magnetic fields setting one memory element to the parallel state and the other memory element to the antiparallel state. Alternatively, ternary information is stored, two of the ternary values being stored in the same way as the binary values, and the third ternary value being stored by setting both memory elements to the same state. The stored values are read by comparing the resistances of the two memory elements.

Abstract: The present invention relates to a data write control method for writing at least two types of data to memory. A multi-valued memory to which information composed of two values can be written per cell and information composed of three or more values can be also written per cell is used as the memory. When at least two types of data are written to the multi-valued memory, the amount of information to be written per cell in the multi-valued memory is controlled depending on the type of the data.

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract: An apparatus determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

Abstract: To switch redundancy circuit properly by performing tests by equipment itself such as semiconductor unit or computer containing semiconductor unit, etc. without using any expensive laser unit. Relieves failure by controlling selectors SEL1 to SEL4 with control memory cells C11 to C14 connected respectively to a plural number of external bit lines OBL1 to OBL4 and by switching the relation of correspondence between the external bit lines OBL1 to OBL4 and the internal bit lines BL1 to BL5. The data to the control memory cells C11 to C14 is given from the external bit lines OBL1 to OBL4.

Abstract: A semiconductor device which is capable of storing n-bits in a unit cell by providing said cell with a set of 2.sup.n -1 (n.gtoreq.2) word-lines and switching means connected or not connected to one of the word-lines and by reading data from a unit cell on the basis of an address designated by an activated word-line and a change of a signal in a bit-line according to the activated word-line.

Abstract: An electrically alterable, non-volatile multi-bit memory cell has K.sup.n predetermined memory states (K.sup.n >2), where K is a base of a predetermined number system and n is a number of bits stored per cell. Programming of the cell is verified by selecting a reference signal corresponding to the information to be stored and comparing a signal of the cell with the selected reference signal.

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented.

Abstract: A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.

Abstract: A circuit and method for reducing the leakage current drawn by a transistor when it is inactive. In a first implementation, a circuit selectively drives the gate of a transistor to a voltage level above a source voltage. As a result, the gate-source voltage is reversed and the leakage current flowing through the transistor is substantially reduced. In a second implementation, a circuit selectively biases the well of a transistor to a voltage level above a normal bias voltage. As a result, the voltage-current characteristics of the transistor are modified so that the leakage current is substantially eliminated.

Abstract: A semiconductor memory includes a memory transistor having a gate connected to a word line and having a threshold level selected from a plurality of threshold levels, and a plurality of comparison transistors having gates are respectively connected to the word line, each of the comparison transistor having a threshold level selected from the reference threshold levels and the threshold levels of the comparison transistor being different from each other. The word line is driven respectively to a plurality of voltage levels, and whenever they are driven to respective values of the plurality of voltage levels, the logical level state determined based on the difference between the current flowing in the memory transistor and the current flowing in the transistor circuit is held, and multibit data stored in the memory transistor is output based on the logical level state held.