Abstract: The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes reprogramming the lower page data to the memory cells prior to programming higher page data to the memory cells in a second pass of the multiple-pass programming operation.

Abstract: A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i?1)th time.

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Abstract: A memory includes a plurality of memory cells and a plurality of peripheral circuits. Each memory cell has a first inverter and a second inverter, the first inverter is supplied by a first power supply rail and a second power supply rail, and the second inverter is supplied by a third power supply rail and a fourth power supply rail. A first voltage difference is applied across the first power supply rail and the second power supply rail, a second voltage difference is applied across the third power supply rail and the fourth power supply rail, and the first voltage difference is less than the second voltage difference. The plurality of peripheral circuits use at least one of boosted power supplies corresponding to the second voltage difference and gate-source differentially-driven circuits.

Abstract: The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

Abstract: A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.

Abstract: Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (1), program transistors (5a, 5b) and erase transistors (3a, 3b) serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN1) connected to the program transistor (5a) in a first cell (2a) for performing data programming also serves as a reading bit line in the other second cell (2b) by switching switch transistors (SWa, SWb) so that malfunctions of read transistors (4a, 4b) that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.

Abstract: A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: A lithium ion power battery lossless charger adopts a charging method of overall serial constant-current and monomer parallel constant-voltage to realize lossless charging on lithium ion power batteries. Charging efficiency is close to 100%, and charging and discharging are completely based on the characteristic curve of the battery. All functions of a battery system, a charging system, a discharging system and a maintenance management system are realized only by a simple circuit, and no overcharge, overheating, over discharge, over current or short circuit occurs. The terminal voltages of all monomer batteries are completely equal when charging is finished, and no equalized charging is required.

Abstract: A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ?Vt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ?Vtp?1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.

Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

Abstract: A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

Abstract: A semiconductor display device correcting system includes a control circuit for carrying out gamma correction of a picture signal supplied from the outside and a nonvolatile memory for storing data for gamma correction. The data for gamma correction is prepared for each semiconductor display device, so that excellent gradation display can be made.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.

Abstract: A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. The first inverter and second inverter respectively include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor and a second pull-down transistor. The first pull-down and pull-up transistors each have a drain terminal mutually coupled to form a first node. The second pull-down and pull-up transistors each have a drain terminal mutually coupled to form a second node. The first and second access transistors each have a gate terminal respectively coupled to a first word line and a second word line. When the first word line provides on signals to turn on the first access transistor, the second low voltage supply provides a first differential voltage simultaneously.

Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.

Abstract: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.

Abstract: A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit.

Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

Abstract: One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell uses one step Write operation under either a FN-channel write scheme to increase a paired flash transistor Vt values in positive direction with a desired ?Vt12 ?1V or a FN-edge write scheme to decrease the Vt values in negative direction with a similar desired ?Vt12?1V to write the ?Vt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step. There is no need of Program-Inhibit Voltage (SBPI) to inhibit non-select flash transistor from programming. In addition, this 8T NVSRAM cell uses DRAM-like charge-sensing scheme to detect the ?V on Q and QB nodes of SRAM in which is coupled and generated from the ?Vt12 stored in MC1 and MC2 flash transistors.

Abstract: A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the precharge unit by sensing the voltage of the precharge voltage terminal. The precharge circuit may control a precharge operation by sensing a change in the voltage level of the precharge voltage terminal.

Abstract: A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node, and a second nonvolatile section coupled to a second data node; and each nonvolatile section including at least one switch element in series with a programmable nonvolatile element, the switch element configured to couple the nonvolatile element to the corresponding data node during a high reliability read operation of the memory cell.

Abstract: A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells.

Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M?1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M?1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract: A nonvolatile memory device comprises a bulk region and a plurality of memory cells connected to a source line and a plurality of wordlines. The method comprises applying a source line voltage to the source line with a first magnitude, applying a bulk voltage to the bulk region with a second magnitude lower than the first magnitude, and performing access operations on the plurality of memory cells while maintaining a substantially constant difference between the bulk voltage and the source line voltage.

Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.

Abstract: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract: Some embodiments relate to a differential memory cell. The memory cell includes a first transistor having a source, a drain, a gate, and a body. A first capacitor has a first plate and a second plate, wherein the first plate is coupled to the gate of the first transistor and extends over the body region. The memory cell also includes a second transistor having a source, a drain, a gate, and a body, wherein the source and body of the second transistor is coupled to the second plate of the first capacitor. A second capacitor has a third plate and a fourth plate, wherein the third plate is coupled to the gate of the second transistor and the fourth plate is coupled to the source and the body of the first transistor.

Abstract: A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including a device region which is isolated by a device isolation film, a first conductive layer provided on the device region via a gate insulation film, an inter-gate insulation film provided on the first conductive layer and including an opening on the first conductive layer, a second conductive layer disposed over the device region and the device isolation film via the inter-gate insulation film, a third conductive layer provided on the first conductive layer, isolated from the second conductive layer by a peripheral trench, and connected to the first conductive layer via the opening of the inter-gate insulation film, and source/drain diffusion layers provided, spaced apart, in the device region in a manner to sandwich the first conductive layer.

Abstract: The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract: A memory cell includes a non-volatile p-channel transistor having a source coupled to a first potential, a drain, and a gate. A non-volatile n-channel transistor has a source coupled to a second potential, a drain, and a gate. A switch transistor has a gate coupled to a switch node, a source, and a drain. A stress transistor has a source and drain coupled between the drain of the non-volatile p-channel transistor and the drain of the non-volatile n-channel transistor, the stress transistor having a gate coupled to a gate bias circuit. Where one of the first or second potentials is a bit line, an isolation transistor is coupled between the other of the second potentials and one of the non-volatile transistors.

Abstract: A memory device has a pair of conductive layers and an organic compound having a liquid crystal property that is interposed between the pair of conductive layers. Data is recorded in the memory device by applying a first voltage to the pair of conductive layers and heating the organic compound, to cause a phase change of the organic compound from a first phase to a second phase.

Abstract: A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.

Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.

Abstract: A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address.

Abstract: A semiconductor integrated circuit including a nonvolatile memory cell is provided with a detection/word line voltage control circuit for sequentially supplying two or more mutually different unstable bit detecting voltages to a control gate of the nonvolatile memory cell to cause the nonvolatile memory cell to output a plurality of pieces of readout data, and an OK/NG determination circuit for comparing the plurality of pieces of readout data to determine whether the nonvolatile memory cell is stable or not.

Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.