Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

Abstract: A memory device is provided. The memory device includes a memory array, operation circuitry configured to perform a memory operation in the memory array in response to a command received from a connected host device, and delay circuitry configured to delay the performance of the memory operation in response to one or more bits received with the command. The one or more bits indicate a duration by which to delay the performance of the memory operation.

Abstract: A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.

Abstract: A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.

Abstract: A data processing system includes a backup nonvolatile memory (NVM), a random access memory (RAM), and a controller. The RAM includes a plurality of partitions, each partition having a different corresponding backup frequency. The controller is configured to back up the contents of each partition of the RAM to the backup NVM in accordance with the corresponding backup frequency.

Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.

Abstract: Technologies are provided for remotely destroying a storage device. One or more commands can be transmitted to a storage device to render the storage device inoperable. The storage device can be placed in a retired operation mode, in which the storage device cannot process data access commands. Data stored in the storage device can be sanitized to prevent it from being retrieved. Code modules that are responsible for processing data access commands can be erased from a firmware of the storage device. The storage device can perform operations to render a storage medium of the storage device inoperable. While in the retired mode, the storage device can process an inquiry command to retrieve information about the storage device from the firmware of the storage device. The retrieved information can be used to generate a digital destruction certificate that can be provided to a supplier of the storage device.

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract: A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.

Abstract: A system of processing a task based on information of frequently used algorithms learned through a memory unit includes a first memory, a second memory, a processor, and a reading unit. The processor processes a first type of task using a first algorithm, and writes to a first memory cell of the second memory. The second memory including first and second memory cells each having a charge storage element. The first and second memory cells correspond to the first and second algorithms, respectively. The reading unit senses a first voltage stored in the first memory cell and a second voltage stored in the second memory cell, and provides information of frequently used algorithms to the processing device based on the sensed first and second voltages.

Abstract: A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.

Abstract: A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers.

Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

Abstract: The present invention provides a method for constructing an NVRAM-based efficient file system, including the following steps: S1. determining a file operation type of the file system, where the file operation type includes a file read operation, a non-persistent file write operation, and a persistent file write operation; and S2. if the file operation type is a non-persistent file write operation, writing, by the file system, content of the non-persistent file write operation to a dynamic random access memory DRAM, updating a corresponding DRAM cache block index, and flushing, at a preset time point, the content of the non-persistent file write operation back to a non-volatile random access memory NVRAM asynchronously, or otherwise, copying, by the file system, related data directly between the NVRAM/DRAM and the user buffer.

Abstract: A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The high voltage device includes a substrate prepared with a device isolation region. The device isolation region defines a device region. The device region includes at least first and second source/drain regions and a gate region defined thereon. A device well is disposed in the device region. The device well encompasses the at least first and second source/drain regions. A primary gate and at least one secondary gate adjacent to the primary gate are disposed in the gate region. The at least first and second source/drain regions are displaced from first and second sides of the primary gate.

Abstract: A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract: Various implementations described herein are directed to a circuit for memory applications. The circuit may include a data storage structure having column multiplexor transistors coupled to complementary bitlines. The circuit may include a wordline shape enhancer having a pair of passgate transistors coupled between the complementary bitlines and a capacitive load.

Abstract: A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows in each of the banks; and an address latch circuit configured to latch a full address specifying one of the word lines, the full address including a first address and a second address. The address latch circuit receives a first command and a second command to latch the first address and the second address in accordance with the first command and the second command, respectively. Paths for the first address and the second address are configured to be separate from each other.

Abstract: A Field Sub-bitline NOR-type (FSNOR) flash array and its operating methods are disclosed. In contrast to the conventional NOR flash array, the FSNOR array is configured in column with multiple 90° rotated NOR pairs linked by field side sub-bitlines to achieve the minimum 4F2 cell size. The FSNOR flash array is divided into multiple sectors by selection transistors for connecting the even/odd sub-bitlines to the global main first metal bitlines. For each FSNOR sector, the two drain electrodes of column-adjacent NOR pairs form the even/odd sub-bitlines separated by trench field oxides respectively, and the common source electrodes of NOR pairs in a column form the common diffusion source lines tied with metal contacts connected to the first metal common source lines. The FSNOR flash array design has enhanced the electrical isolation of the selected NVM cell devices from the unselected NVM cell devices.

Abstract: A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

Abstract: A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.

Abstract: A configuration memory includes: memory cell including first and second MISFETs, each of the first and second MISFETs having a gate insulating layer, a source, a drain, and a gate, one of the source and the drain of the first MISFET being connected to a first bit line, the gate of the first MISFET being connected to a first word line, one of the source and the drain of the second MISFET being connected to a second bit line, the gate of the second MISFET being connected to the first word line; a sense amplifier having an output terminal and connected to the first and second bit lines; and a control circuit which is configured to write data in the memory cell by injecting carriers in the gate insulating layer of the first MISFET.

Abstract: A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process.

Abstract: The invention concerns a memory cell comprising: first and second resistive elements (202, 204), at least one of which can be programmed to adopt at least two resistive states (Rmin Rmax); the first resistive element (202) being coupled between a first storage node (206) and a first intermediate node (208), the second resistive element (204) being coupled between a second storage node (210) and a second intermediate node (212); a transistor (220) coupled between the first and second intermediate nodes; and a control circuit arranged to activate the transistor while a second supply voltage (VDD, GND) is being applied to the first or second storage node to generate a programming current in a selected direction through the first and second resistive elements in order to program the resistive state of at least one of the elements.

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region.

Abstract: A nonvolatile memory device includes a pair of MIS transistors one of which is placed in a programmed state by a first program operation utilizing a hot carrier effect to store one-bit data in the pair of MIS transistors, and a control unit configured to recall the one-bit data from the pair of MIS transistors in a recall operation, to cause an unprogrammed one of the MIS transistors to be placed in a programmed state by a second program operation utilizing a hot carrier effect in response to the one-bit data recalled from the pair of MIS transistors, and to erase the programmed states of both of the MIS transistors in an erase operation.

Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

Abstract: An operation unit-equipped device includes a generator that generates an application module including a processing executor that executes a processing, a display part that performs a display appropriated to the processing executor, and a controller that controls the processing executor and the display part; and a discard requester that requests, when at least one new processing executor and one new display part are generated after the generation of the processing executor and the display part, a discard of the processing executor and the display part generated previously. When there is an active processing in the processing executor generated previously when the request for discard is made, the controller discards the display part generated previously and maintains the processing executor generated previously until the active processing is completed, and discards the processing executor generated previously when the active processing in the processing executor generated previously is completed.

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Abstract: A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from a lower level memory layer.

Abstract: A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.

Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

Abstract: A memory system and a method of operating the same are provided. The method includes reading least significant bit (LSB) data of a first physical page based on a first pre-read voltage and performing a most significant bit (MSB) program based on the LSB data of the first physical page when the MSB program is performed on the first physical page, defining a management area by comparing the number of error bits included in MSB data of the first physical page with a first threshold value, preforming an LSB program on a second physical page of the management area, reading LSB data of the second physical page based on a second pre-read voltage, which is lower than the first pre-read voltage, and performing the MSB program on the second physical page based on the LSB data of the second physical page.

Abstract: This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

Abstract: A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor.

Abstract: Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.

Abstract: A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell provided in a ROM area, a first read voltage to a first selected word line, and apply a first read pass voltage lower than a second read pass voltage to a first non-selected word line, thus allowing for the ROM area reading operation of reading a threshold voltage set in the first selected memory cell. The control circuit is configured to apply, when reading data of a second selected memory cell provided in a normal storage area, a second read voltage to a second selected word line, and apply the second read pass voltage to a second non-selected word line, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell.

Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

Abstract: A controller includes a memory test logic circuit to detect a malfunctioning row of primary data storage elements within an external memory device, an internal memory to store an address corresponding to the malfunctioning row of the external memory device, and a memory setup logic circuit to initiate a repair mode in the external memory device and to end the repair mode in the external memory device. The controller further includes a port to couple to an address line to transmit the address corresponding to the malfunctioning row of the external memory device.