Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract: A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer.

Abstract: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract: A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.

Abstract: A memory device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

Abstract: A semiconductor device includes a main active region provided in a semiconductor substrate and having a first side surface and a second side surface facing each other. A first auxiliary active region adjacent the first side surface of the main active region and spaced apart from the main active region by a first distance is provided. A second auxiliary active region adjacent the second side surface of the main active region and spaced apart from the main active region by the first distance is provided. A first conductive pattern crosses the main active region and includes first and second side portions facing each other. The first side portion of the conductive pattern is disposed between the first auxiliary active region and the main active region, and the second side portion of the conductive pattern is disposed between the second auxiliary active region and the main active region.

Abstract: A logic module includes a device for implementing a logic function the device including at least one input and at least one output, the output at least partially representing the result of the logic function; at least one first element including at least one resistance state, at least one second element formed by a bipolar resistive memory; the first element and the second element having a common electrode connected to the output.

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract: A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate.

Abstract: The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted.

Abstract: According to an embodiment, a semiconductor storage device includes an SRAM cell. The SRAM cell includes first and second transfer gates each comprising a pass gate. The pass gate includes first and second tunnel transistors. The first tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region, and a gate electrode supplied with a control voltage. The second tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region electrically connected to the second diffusion region of the first tunnel transistor, and a gate electrode electrically connected to the gate electrode of the first tunnel transistor.

Abstract: A register for a scan test has a data saving function. A scan flipflop includes first to third memory circuits. The first memory circuit is a memory circuit functioning as a register of a combination circuit in normal operation. The second memory circuit is a memory circuit for backup of the first memory circuit. The third memory circuit has a function of transferring data to a flipflop in a next stage. Further, the second memory circuit has a function of writing data of the first memory circuit to the third memory circuit and a function of writing data of the third memory circuit to the first memory circuit. At a given time, data of the first memory circuit can be extracted from an external device and data can be stored in the first memory circuit from an external device.

Abstract: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.

Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: A nonvolatile memory system can include a nonvolatile memory device that can be configured to store data and a nonvolatile memory buffer circuit that can be configured to store data of a type that is predetermined to be flushed to the nonvolatile memory device in a sudden power off backup operation of the nonvolatile memory system, whereas a volatile memory buffer circuit can be configured to store other data of a type that is not to be flushed to the nonvolatile memory device in the sudden power off backup operation of the nonvolatile memory system.

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Abstract: Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.

Abstract: The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A method includes, in a data storage device, receiving a read command to read a portion of a wordline of a memory. The method also includes determining a first and a last storage element of the wordline to identify a set of storage elements. The method includes determining a first set and a second set of sense amplifiers of multiple sense amplifiers coupled to the wordline. The first set of sense amplifiers is coupled to the set of storage elements and the second set of sense amplifiers is coupled to one or more storage elements of the wordline other than the first set of storage elements. The method includes reading data by applying a read voltage to the wordline and providing a sense enable signal to each sense amplifier of the first set of sense amplifiers while each sense amplifier of the second set of sense amplifiers is disabled.

Abstract: A non-volatile semiconductor memory device has memory cell arrays, with the memory cells arranged in a matrix configuration and divided into p areas in the column direction, a column redundancy area arranged in a portion of the memory cell array and having redundancy columns that can substitute for defective user data columns, and a column substituting register that holds the column substituting information for substituting the defective user data columns of the selected area with the redundancy columns.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: The present invention discloses two preferred embodiments of a 12T NVSRAM cell with a flash-based Charger and a pseudo 10T NVSRAM cell with one shared Flash-based Charger. The Flash-based Charger can be made of a 2-poly floating-gate type or a 1-poly charge-trapping SONOS/MONOS flash type, regardless of PMOS type or NMOS type. In an alternative embodiment, the Store operation of above two preferred NVSRAM cell use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower associated with Flash Charger and 2-step SRAM amplification technique to amplify the threshold level difference ?Vt stored in the paired Flash transistors. The ?Vt can be detected as low as 1V when the coupled charges through the Flash charger are sufficient by ramping a gate control of the Flash Charger as high as VPP or by increasing the channel length for the Flash Charger.

Abstract: The operating method of a data storage device includes storing data in a buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of a memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to a multi-bit memory device based on the determined program pattern.

Abstract: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.

Abstract: The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ?VQ-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.

Abstract: Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most significant bit (MSB) latch of the multi-level memory cell and/or between the auxiliary latch and a least significant bit (LSB) latch of the multi-level memory cell while programming the multi-level memory cell.

Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

Abstract: Three-dimensional NAND stacked memory devices are described that include a stack including alternating word line and dielectric layers and a plurality of NAND strings of memory cells formed in memory holes which extend through the layers. Each memory cell includes a control gate formed by one of the word line layers, and multiple selector devices, each selector device coupled to an end of a corresponding NAND string. The NAND strings are disposed above a substrate, and the selector devices are disposed in the substrate.

Abstract: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes programming information to the non-volatile memory. The information includes multiple codewords. The method further includes accessing a sample codeword of the multiple codewords from the non-volatile memory and determining an error rate associated with the sample codeword. The error rate is determined by an error correcting code (ECC) engine. The method further includes programming the information at the non-volatile memory in response to the error rate satisfying an error threshold.

Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

Abstract: One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell uses one step Write operation under either a FN-channel write scheme to increase a paired flash transistor Vt values in positive direction with a desired ?Vt12 ?1V or a FN-edge write scheme to decrease the Vt values in negative direction with a similar desired ?Vt12?1V to write the ?Vt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step. There is no need of Program-Inhibit Voltage (SBPI) to inhibit non-select flash transistor from programming. In addition, this 8T NVSRAM cell uses DRAM-like charge-sensing scheme to detect the ?V on Q and QB nodes of SRAM in which is coupled and generated from the ?Vt12 stored in MC1 and MC2 flash transistors.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal.

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.