Abstract: A memory cell array of a nonvolatile semiconductor memory device includes a plurality of memory cells disposed in a row direction and a column direction. The memory cell array includes a plurality of word lines. Each of the memory cells includes a source region and a drain region. Each of the memory cells includes a select gate and a word gate which are disposed to face a channel region between the source region and the drain region. Each of the memory cells includes a nonvolatile memory element formed between the word gate and the channel region. The word line drive section includes a plurality of unit word line drive sections. Each of the unit word line driver sections drives two of the word lines connected respectively with two of the word gates adjacent to each other in the column direction.

Abstract: A semiconductor capacitance device includes a P-type semiconductor layer, an N-type well region which is provided in the P-type semiconductor layer, and a P-type well region which is provided in the N-type well region. Further, the semiconductor capacitance device includes a gate electrode layer which is provided over the P-type well region with an insulating layer interposed therebetween, a first N-type impurity layer which is provided in the P-type well region on one side of the gate electrode layer, and a second N-type impurity layer which is provided in the P-type well region on the other side of the gate electrode layer. The gate electrode layer has at least one through hole, and a third N-type impurity layer is provided in the P-type well region at a position facing the through hole.

Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.

Abstract: A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.

Abstract: A semiconductor memory device is constituted by forming two types of insulation films on the channel of an MOS transistor on which a vertical type another MOS transistor using the control gate of the MOS transistor as a substrate is stacked. Thus, a non-volatile semiconductor memory device small in size, having high reliability, high density, excellent fatigue and a random access function can be provided.

Abstract: The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile memory cells, with special emphasis on source-side injection flash EEPROM cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an “internal P-well” within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive.

Abstract: To suppress or prevent the so-called write disturbance phenomenon from occurring in write-disabled non-selected memories in a semiconductor device provided with a plurality of memory cells, in any selected one of which data can be written electrically by means of the so-called tunneling phenomenon. In a flash memory that can disable writing of data by suppressing injection of electrons in the accumulation layer of each non-selected memory cell in which data is to be written with a writing disable voltage applied to the drain thereof before a write voltage is applied to the control gate electrode of each selected memory cell, the relationship among a writing disable voltage Vwd, a read voltage Vr applied to the drain of a selected memory cell from which data is to be read, and a punch-through withstand voltage BVds between the source and the drain of each selected memory cell is set so as to satisfy Vr<BVds<Vwd.

Abstract: A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons. The present invention includes cells which have minimal injection of non-channel electrons therein.

Abstract: In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line.

Abstract: A nonvolatile memory device having a lightly doped source and a method for manufacturing the same are provided. In the nonvolatile memory device, a first insulating layer, a floating gate, a second insulating layer and a control gate are sequentially formed on a semiconductor substrate, and a drain, a lightly doped source and a highly doped source are formed around a surface of the semiconductor substrate. At this time, the highly doped source is shallower than the drain without being overlapped by the floating gate. Thus, the integration of the memory cell can be increased, and the trapping of electrons is reduced in the first insulating layer formed between the floating gate and the lightly doped source, to thereby enhance the characteristics of the memory cell.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.

Abstract: A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The ramped reference voltage signal is applied to a differential amplifier connected to a reference circuit to produce a ramped erase voltage signal. The ramped erase voltage signal is then applied to sources of the memory cells during an erase operation. Both analog and digital circuits are described for generating the ramped reference voltage signal.

Abstract: A nonvolatile memory device having a lightly doped source and a method for manufacturing the same are provided. In the nonvolatile memory device, a first insulating layer, a floating gate, a second insulating layer and a control gate are sequentially formed on a semiconductor substrate, and a drain, a lightly doped source and a highly doped source are formed around a surface of the semiconductor substrate. At this time, the highly doped source is shallower than the drain without being overlapped by the floating gate. Thus, the integration of the memory cell can be increased, and the trapping of electrons is reduced in the first insulating layer formed between the floating gate and the lightly doped source, to thereby enhance the characteristics of the memory cell.

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.

Abstract: A random access memory cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.

Abstract: A nonvolatile memory device in which an electrically conductive “program assist plate” is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

Abstract: A contacted array of programmable and erasable semiconductor memory devices. Each of the memory devices has a split gate structure, including a source region, a drain region, a channel extending between the source and drain regions, a floating gate extending over a portion of the channel with a first dielectric layer therebetween, a control gate extending over a portion of the floating gate through a second dielectric layer, and a program gate extending above the floating gate with a dielectric layer therebetween. The program gate forms a capacitor with the floating gate with a coupling ratio sufficient to couple a voltage at least as high as the drain voltage to the floating gate, thereby establishing a high voltage at a point in the channel between the control gate and the floating gate and ensuring a high hot-electron injection towards the floating gate.

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.