Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: A calibration module generates a plurality of calibration codes respectively for a first plurality of transistors located along (i) a plurality of bit lines and (ii) a first word line of a memory array. Each of the calibration codes is based on a distance of a corresponding one of the plurality of bit lines from an input of the first word line. A voltage generator outputs a first voltage generated based on a first plurality of codewords to an input of a second word line. A control module determines values of threshold voltages of a second plurality of transistors located along (i) the plurality of bit lines and (ii) the second word line based on (a) the first plurality of codewords and (b) currents sensed through the second plurality of transistors, and adjusts the values of the threshold voltages based on the calibration codes.

Abstract: A storage element capable of retaining data even after supply of power supply voltage is stopped is provided. In the storage element retaining data in synchronization with a clock signal, with the use of a capacitor and a transistor having a channel in an oxide semiconductor layer, the data can be retained even after supply of power supply voltage is stopped. Here, when the transistor is turned off while the level of the clock signal is kept constant before the supply of power supply voltage is stopped, the data can be retained accurately in the capacitor. By applying such a storage element to each of a CPU, a memory, and a peripheral control device, supply of power supply voltage can be stopped in the entire system, so that the power consumption of the entire system can be reduced.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined.

Abstract: A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202-205 each having internal power supplies is contained in an enclosure 201. Integrated circuits 202-205 are described showing how to make external connection to internal power supplies. Connections 208-212 are provided to the internal power supplies of each of devices 202-205. Another embodiment 500 of the system provides for disablement of regulators in multiple integrated circuits 502, 503, and 504 by another integrated circuit 501 for power consumption reduction. The method FIG. 6 includes providing devices and connecting the internal power supplies together. An integrated circuit 501 with a power supply 400 adapted to the system and method with additional circuitry 308, 404 and 402 for disabling a regulator 306 is described.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectric material having a switchable spontaneous polarization, and a second semiconductor material having a spontaneous polarization, the resistive ferroelectric material being positioned between and in contact with the first and second semiconductor materials. The memory device can be configured to store energy that can be released by applying a voltage pulse to the memory device.

Abstract: A voltage generating system and a memory device using the same are disclosed. The voltage generating system includes an internal voltage regulator, configured to supply a current to pull an internal supply voltage to a regulated level and maintain at the regulated level; and a substrate-bias controlled selector, configured to receive a regulator power-up mode signal, a regulating mode signal and a substrate-bias voltage of a substrate, and control the internal voltage regulator such that when the substrate-bias voltage is smaller than a predetermined voltage, the internal voltage regulator powers up and operates normally by respectively taking the regulator power-up mode signal and the regulating mode signal into consideration, and when the substrate-bias voltage is larger than or equal to the predetermined voltage, the internal voltage regulator is disabled. The predetermined voltage is smaller than or equal to a forward voltage of a p-n junction formed with the substrate.

Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

Abstract: Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to a constant current driver, which works in tandem with the VCP pad or external pin to perform massive parallel read or write operations. The inventive concepts include fast test setup and initialization of the memory array. The data can be retention tested or otherwise verified using similar massive parallel testing techniques. Embodiments also include a memory test system including a memory device having DFT circuitry configured to perform massive parallel stress testing, retention testing, functional testing, and test setup and initialization.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.

Abstract: A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.

Abstract: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and a corresponding one of the pair of bit lines. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the corresponding bit line and configured to maintain a voltage level of the corresponding bit line. The noise threshold control circuit is connected to the sense amplifier output and the pair of bit lines. The noise threshold control circuit comprises a half-Schmitt trigger circuit or a Schmitt trigger circuit.

Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

Abstract: A voltage reference circuit includes a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground. A second depletion-mode PMOS transistor is coupled to the first enhancement PMOS transistor to form a feedback circuit. A first resistive device is coupled between the voltage supply and the second depletion-mode PMOS transistor, and a second resistive device is coupled between the second depletion-mode PMOS transistor and the ground. A bias circuit is coupled to a gate of the first enhancement-mode NMOS transistor. The first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region. A first reference voltage across the first resistor and a second reference voltage across the second resistor are configured to be independent of the magnitude of the voltage supply and have low temperature drift.

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract: A voltage driving circuit comprises a current bias generating unit and a voltage driving unit. The current bias generating unit is configured to receive a mode signal and to generate a mode selection current in response to the mode signal. The voltage driving unit is coupled to the current bias generating unit, and is configured to receive the mode selection current and to drive an output voltage at a slew rate that is set according to the mode selection current. The voltage driving unit can include a plurality of stages, where each stage is configured to drive the output voltage at a respective different slew rate according to the mode signal.

Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state.

Abstract: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period.

Abstract: A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of a precision resistor disposed outside the semiconductor memory device; comparing the reference current with the first current; comparing the reference current with the second current; programming the reference cell if the value of the reference current is greater than that of the first current; and erasing the reference cell if the value of the reference current is less than that of the second current. The value of the second current is less than that of the first current.

Abstract: A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.

Abstract: Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract: Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a module configured to cause a first current from a first current source and a second current from a second current source to flow through a selected memory cell among the memory cells during an operation of storing information in the selected memory cell. Other embodiments including additional apparatuses and methods are described.

Abstract: A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.

Abstract: Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines.

Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

Abstract: A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line, and a second data line. The second type is different from the first type. The first data line is coupled with a first terminal of the sense amplifier. The second data line is coupled with a second terminal of the sense amplifier. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage.

Abstract: An operation method of a semiconductor memory device includes forming a first data distribution by performing a first programming operation during a first write operation, outputting a predetermined data by detecting the first data distribution on the basis of a first reference voltage corresponding to the first programming operation during a first read operation, forming a second data distribution by performing a second programming operation during a second write operation, and outputting data that is the same as the predetermined data corresponding to the first data distribution during the first read operation by detecting the second data distribution on the basis of a second reference voltage corresponding to the second programming operation during a second read operation.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.

Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.

Abstract: A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Abstract: A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line and a sense amplifying ground line, respectively, and sense-amplify data loaded on a pair of data lines, and a pre-charging unit configured to pre-charge and equalize the sense amplifying power source line and the sense amplifying ground line with a sense amplifying pre-charge voltage, generate the sense amplifying pre-charge voltage by voltage dividing the sense amplifying power source voltage and the sense amplifying ground voltage through a voltage dividing path including the sense amplifying power source line and the sense amplifying ground line, and apply the sense amplifying power source voltage to the sense amplifying power source line and the sense amplifying ground voltage to the sense amplifying ground line in response to a sense amplifying pre-charge control signal.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.