Abstract: In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mV) relative to the nominal supply level (e.g., 1.2V). Each sense amplifier has a trans-impedance amplifier that converts a memory bit-line current into a voltage level indicative of whether a selected memory cell is programmed or erased. The trans-impedance amplifier has a current mirror with a high-threshold regeneration device that lowers the sense amplifier's range of operating voltages. Each sense amplifier also has a level-shifted inverter that further lowers the sense amplifier's operating voltage range.

Abstract: A power-up signal generation circuit includes a first driving section configured to generate a pre-power-up signal by driving a first node to a first pull-up drivability or driving the first node to a first pull-down drivability in response to an internal voltage when not in an active mode, and a second driving section configured to generate the pre-power-up signal by driving the first node to a second pull-up drivability or driving the first node to a second pull-down drivability in response to the internal voltage in the active mode. The first pull-up drivability is larger than the second pull-up drivability, and the first pull-down drivability is smaller than the second pull-down drivability.

Abstract: Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.

Abstract: A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from an external device, based on a reference signal provided from the external device; and a control logic configured to control an operation for the memory cell according to the generated control signals.

Abstract: A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a plurality of signal lines, and a plurality of signal-line-lead-out portions. In the memory cell array, a plurality of memory cells are arranged. The plurality of signal lines connected to the plurality of memory cells. The plurality of signal-line-lead-out portions are arranged in a periphery of the memory cell array and are connected to the plurality of signal lines. Each of the plurality of signal-line-lead-out portions includes a plug as an electrode whose upper surface and side surface are covered with a passivation film.

Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A storage subsystem implements a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table.

Abstract: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes.

Abstract: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.

Abstract: A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage.

Abstract: A system including a reference voltage module to generate one or more reference voltages used to determine states of a plurality of memory cells of a nonvolatile memory. The memory cells have a threshold voltage distribution. A divider module selects, in response to a change in the threshold voltage distribution, a voltage range within which to update one of the reference voltages, and divide the voltage range into a plurality of regions. A counting module counts a number of the memory cells having threshold voltages within each of the plurality of regions. An update module selects one of the plurality of regions having the threshold voltages of a smallest number of the memory cells, and updates the one of the reference voltages to a voltage value associated with the selected one of the plurality of regions to compensate for the change in the threshold voltage distribution.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

Abstract: A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the stored positive charges to a ground voltage to generate a negative high voltage having a magnitude larger than a magnitude of the supply voltage.

Abstract: A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

Abstract: Devices and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.

Abstract: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.

Abstract: Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.

Abstract: A nonvolatile semiconductor memory includes a first power supply voltage pad to which a first power supply voltage required for a writing, reading or erasing operation of the memory cells is applied. The nonvolatile semiconductor memory includes a second power supply voltage pad to which a second power supply voltage that is lower than the first power supply voltage and to be supplied to the I/O circuit is applied. The nonvolatile semiconductor memory includes a first voltage down-converting circuit that converts the first power supply voltage down to a first down-converted voltage that is higher than the second power supply voltage. The nonvolatile semiconductor memory includes a second voltage down-converting circuit that converts the second power supply voltage down to a second down-converted voltage that is lower than the first down-converted voltage.

Abstract: A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

Abstract: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros.

Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Abstract: Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.

Abstract: Integrated circuits with memory circuitry are provided. The memory circuitry may include rows of data line segments. Each data line segment may have associated memory cells, a programmable-strength precharge circuit, a latch circuit, a programmable-strength pull-up circuit, and a data line segment buffer. The precharge circuit may include multiple paths that can be switched into use depending on the configuration of programmable bits. The programmable-strength pull-up circuit may include multiple pull-up paths. The number of pull-up paths in use can be configured. The latch circuit may include a latch inverter that enables the programmable latch circuit during precharge operations. During a precharge period, the latch circuit can be disabled to block contending pull-down current and the data line segment buffer can be disabled to avoid crossbar currents.

Abstract: A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

Abstract: Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Abstract: Integrated circuits with voltage regulation circuitry are provided. Voltage regulation circuitry may be powered by a core supply voltage and may not have a bandgap reference circuit. Voltage regulation circuitry may have an error amplifier in a negative feedback configuration. The error amplifier may have inputs connected to reference voltages generated by resistor strings. The resistor strings may be trimmable to provide a desired negative voltage. The desired negative voltage may be fed to the gates of transistors to help reduce leakage. The desired negative voltage may be have improved tolerance to process-voltage-temperature variations and may improve the reliability of transistors.

Abstract: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed between the controller chip and the integrated circuit chip to transfer a first signal and a second speed signal, wherein the first signal has a higher frequency than the second signal, and a status channel formed between the controller chip and the integrated circuit chip to transfer at least one status signal, wherein the integrated circuit chip is configured to select one of the first buffer and the second buffer and actives the selected buffer in response to the at least one status signal and receive a signal transferred through the I/O channel.

Abstract: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.

Abstract: A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.

Abstract: A memory array including at least one cross-latched pair of transistors for storing data. The memory array further includes a first power line for supplying a first reference voltage and a second power line for supplying a second reference voltage. The memory array further includes a first switch having a first output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the first power line. The memory array further includes a second switch having a second output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the second power line. The first output is coupled to the second output.

Abstract: A pump circuit includes a plurality of clock control circuits configured to transfer a clock to respective output terminals in response to respective pump-off signals or block the clock from being transferred to the respective output terminals, a plurality of charge pumps configured to generate respective high voltages by performing respective pumping operations in response to respective clock signals of the output terminals, and a plurality of switching circuits configured to transfer the respective high voltages to a final output terminal in response to respective control signals.

Abstract: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.

Abstract: A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.

Abstract: A semiconductor memory apparatus includes a plurality of mats each having a plurality of memory cells coupled to intersections between a plurality of word lines and bit lines which are arranged to cross each other, wherein a word line boosting voltage or negative word line voltage is driven onto a word line, depending on whether the corresponding word line is selected or not, and the negative word line voltage driven to a mat including the selected word line has a lower level than the negative word line voltage driven to a mat which does not include the selected word line.

Abstract: Power supplied to a memory module is provided. A first voltage is supplied to a first power distribution pathway, the first voltage being from a voltage supplied to a printed circuit board on which the memory module resides. A second voltage is generated, the second voltage being generated by a voltage regulator. The second voltage is supplied to a second power distribution pathway.

Abstract: A period signal generation circuit includes a period signal generator configured to alternately charge and discharge a control node according to a level of the control node to generate a period signal, a discharge controller configured to discharge a first current having a constant value from the control node in response to a temperature signal and discharge a second current varying according to an internal temperature thereof from the control node in response to the temperature signal, and a tester configured to control a charging speed and a discharging speed of the control node.

Abstract: A period signal generation circuit includes a first discharger configured to discharge first current having a constant value from a control node in response to a temperature signal; and a second discharger configured to discharge second current varying according to an internal temperature thereof from the control node in response to the temperature signal.

Abstract: A period signal generation circuit includes a first discharger configured to discharge first current from a control node which is driven in response to a first reference voltage, and a second discharger configured to discharge second current from the control node. The total current of the first and second currents is substantially constant when an internal temperature of the discharge controller is below a predetermined temperature, and the total current of the first and second currents varies as the internal temperature increases over the predetermined temperature.

Abstract: To prevent the influence of variations in reference voltage until a power source is activated in a semiconductor device including a reference voltage generating circuit that can be adjusted by trimming data. In a semiconductor device, a reference voltage generating unit generates a first reference voltage adjusted in accordance with trimming data and a second reference voltage that does not depend on the trimming data based on an external power source voltage. A nonvolatile memory operates in accordance with a voltage based on the first reference voltage and stores the trimming data. A power-on reset circuit switches logic levels of a reset signal when the external power source voltage reaches a constant multiple of the second reference voltage at the time of activation of power source. A control circuit causes the reference voltage generating unit to read the trimming data stored in the nonvolatile memory in response to the switching of the logic levels of the reset signal.

Abstract: A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array.

Abstract: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.