Abstract: A controller includes: a processor suitable for controlling a memory device to read map data stored in a memory and read out a physical address corresponding to data requested by a host to be read; a counter suitable for obtaining reliability information on the map data stored in the memory; a determining unit suitable for activating a pre-pumping mode when reliability of the map data is poor; a deciding unit suitable for determining a first target die of a pre-pumping operation for reading the data in the activated pre-pumping mode; and a pumping unit suitable for controlling the memory device to perform the pre-pumping operation on the first target die during a background operation for reading out the physical address.

Abstract: A control unit included in a PLC generates power-cut retaining information to be retained at a power cut, and stores the generated power-cut retaining information into a main memory. The control unit includes a file system unit for reading and writing target information from and into a nonvolatile memory. When the file system unit receives a power cut notification indicating a cut of power fed while reading or writing target information from or into a nonvolatile memory, the file system unit stops the reading or writing process, and writes the power-cut retaining information stored in the main memory into the nonvolatile memory using power fed from the auxiliary power supply.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.

Abstract: A flash memory device includes a first memory cell, a second memory cell, a row decoder, and a bias generator. The first memory cell is a selected memory cell, and the second memory cell is an unselected memory cell connected with a bit line that is connected to the first memory cell. The row decoder controls a word line voltage to be applied to the first memory cell and controls an unselected source line voltage to be applied to the second memory cell. The bias generator generates the word line voltage based on a threshold voltage of a word line transistor changing with an ambient temperature and generates the unselected source line voltage based on a voltage level of the selected bit line.

Abstract: There are provided a signal generation circuit and a semiconductor memory device including the same. The signal generation circuit includes: a signal input component configured to generate a first internal output signal and a second internal output signal in response to an input signal, and to adjust potential levels of the first internal output signal and the second internal output signal in response to an output signal; and a signal output component configured to generate the output signal in response to the first internal output signal and the second internal output signal.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Abstract: According to one embodiment, a semiconductor storage device comprises a first memory cell including a first resistance change element; a first bit line and a first source line coupled to the first memory cell; and a first resistance coupled to at least one of the first bit line and the first source line.

Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Abstract: Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

Abstract: A controller includes an input/output circuit and a reference voltage generating circuit. The input/output circuit includes a plurality of receiving circuits. Each receiving circuit receives and processes one data bit and generates an output bit accordingly. The reference voltage generating circuit is coupled to the input/output circuit and includes a plurality of circuit units for providing a plurality of reference voltages. One of the circuit units is coupled to one of the receiving circuits to provide a reference voltage to the corresponding receiving circuit and the receiving circuit processes the data bit according to the received reference voltage.

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Abstract: A memory device includes a memory array, a switch device, and a controller. The switch device is arranged between a first voltage node and a second voltage node. The second voltage node is connected to the memory array. The controller is enabled to output a refresh mode signal, a refresh trigger signal, and a pre-start up signal. The memory device enters a self-refresh mode in response to the refresh mode signal. The memory device performs a self-refresh on the memory array in the self-refresh mode. In self-refresh mode, the controller outputs the pre-start up signal first prior to the refresh trigger signal to enable the switch device, so that the voltage of the second voltage node is increased to the voltage of the first voltage mode.

Abstract: The data storage device includes scale-out storage devices and a controller configured to assign commands to the scale-out storage devices and re-assign the commands assigned to the scale-out storage devices based on state information output from a first scale-out storage device among the scale-out storage devices. Each of the scale-out storage devices includes a volatile memory device, a non-volatile memory device, and a scale-out controller configured to control the volatile memory device and the non-volatile memory device.

Abstract: Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip The first semiconductor chip includes a transmission circuit input unit, a transmission circuit unit, and a transmission unit. The second semiconductor chip includes a reception unit, a reception circuit unit, and a reception circuit output unit. The transmission unit and the reception unit can communicate with each other in a non-contact manner. A transmission circuit unit input signal having a predetermined transmission-side potential is input into the transmission circuit unit. A reception circuit unit input signal is input into the reception circuit unit via the non-contact communication between the transmission unit and the reception unit. The reception circuit unit outputs a reception circuit unit output signal having a predetermined reception-side potential. The ratio of the reception-side potential to the transmission-side potential can be changed.

Abstract: A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages suitable for storing data; and a controller suitable for receiving a plurality of commands from a host, performing a plurality of command executions on the plurality of memory blocks in response to the plurality of commands, checking parameters of the plurality of memory blocks according to the plurality of command executions performed on the plurality of memory blocks, selecting first memory blocks among the plurality of memory blocks according to the parameters, and copying data stored in the first memory blocks to second memory blocks among the plurality of memory blocks.

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Abstract: An RF switch includes two or more coupled RF switch cells, each RF switch cell including a transistor having a first source/drain node, a second source/drain node, and a gate node, a first varactor is coupled between the first source/drain node and the gate node, and a second varactor is coupled between the second source/drain node and the gate node.

Abstract: Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: Storage divisions are selected for garbage collection by use of a first selection criterion that is based on an amount of storage capacity freed by reclaiming the respective storage divisions. The first selection criterion may be overridden by a second, different selection criterion in response to determining that a wear variance of the storage divisions exceeds a threshold. The second selection criterion may select a storage division to reclaim based on a wear-level of the storage division. Overrides of the first selection criterion may be limited to a particular override frequency and/or period. The first selection criterion may comprise a logarithmic comparison of the amount of invalid data within the storage divisions. The amount of invalid data in a storage division may be calculated in terms of recovery blocks, having a size that exceeds the size of the physical storage locations within the storage divisions.

Abstract: In one embodiment, an electronic device includes a power supply circuit that has a first switch circuit between a power supply line and a ground potential. The first switch circuit connects the power supply line to the ground potential upon receipt of a control signal that is supplied when a supply of power on the power supply line is cut off. A capacitor is connected between the power supply line and the ground potential. A second switch circuit is between the capacitor and the power supply line. The second switch circuit is configured to disconnect the capacitor from the power supply line upon receipt of the first control signal. A controller circuit is configured to supply the first control signal when the supply of power on the power supply line is cut off.

Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.

Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.

Abstract: A pressure detecting includes a plurality of sensing cells arranged a plurality of rows and columns, each of the plurality of sensing cells including a pressure sensing element and a selection transistor. First driving signal lines are disposed in the rows, and the first driving signal lines are connected to the selection transistors of a first portion of the plurality of sensing cells in a respective row. Second driving signal lines are disposed in a portion of the plurality of rows, and the second driving signal lines are connected to the selection transistors of a second portion of the plurality of sensing cells in a respective row. First and second driving circuits are respectively connected to the first driving signal lines the second driving signal lines.

Abstract: A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Abstract: The invention provides a CMOS GOA circuit, comprising a signal processing module having a first and a second TFTs, the first TFT having a gate connected to a first control signal, a source connected to an output node and a drain connected to a third node; the second TFT having a gate and a source connected to a second control signal, and a drain connected to the third node; the first and second control signals having opposite phases, the first and second control signals controlling the first and second TFTs to turn on alternatingly inputting a voltage signal of the output node or a second control signal to the third node. Compared to the known technique using NAND circuit, the invention reduces the number of TFTs required by latch module without affecting operation of the circuit, and facilitates the implementation of the ultra-narrow border or borderless display products.

Abstract: The semiconductor memory device includes: a memory cell; a sensing circuit connected to the memory cell via a first bit line and a second bit line different from the first bit line, the sensing circuit configured to sense data stored in the memory cell; and a bit line voltage control circuit connected to the memory cell via the first bit line and the second bit line, the bit line voltage control circuit configured to precharge the first bit line to a first voltage that is lower than a supply voltage and to precharge the second bit line to a second voltage that is lower than the supply voltage and is different from the first voltage.

Abstract: A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode.

Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.

Abstract: A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.

Abstract: A memory system includes a non-volatile memory and a controller configured to perform a read re-try in response to a failed normal read. The read re-try includes a first read of data at a first read voltage, a second read of data at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the first read, a third read of data carried out a plurality of times at a plurality of third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount, and a final read of data at a read voltage that is set closer to the second read voltage than the first read voltage.

Abstract: A voltage system and a method of operating a voltage system are provided. The voltage system includes an oscillator and a pump device. The oscillator is configured to provide an oscillation signal exhibiting a first frequency when a voltage level of a supply voltage is greater than a reference voltage level, and to provide the oscillation signal exhibiting a second frequency greater than the first frequency when the voltage level of the supply voltage is less than the reference voltage level. The pump device is configured to provide the supply voltage, based on a frequency of the oscillation signal provided by the oscillator, by performing a charging operation.

Abstract: Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.

Abstract: A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.

Abstract: The subject technology provides reduced overhead in Low Density Parity Check decoding operations. A method includes receiving a hard decode fail indication that decoding first raw data read from non-volatile memory in response to a first read command using a first set of voltages failed. The first read command comprises a first set of read operations. The method includes issuing to the non-volatile memory a second read command for the data using a second set of voltages. The second read command comprises a second set of read operations. The method includes issuing to the decoder, for processing in parallel with the second read command, at least one soft decoding request using soft information based on the first raw data. The method includes receiving from the decoder a success indication of successful decoding.

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

Abstract: An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

Abstract: Example implementations relate to placing loads in a self-refresh mode using a shared backup power supply. For example, a shared backup power supply system can include a node coupled to a shared backup power supply. The node can include a plurality of loads that include volatile memory and a processing resource to place the plurality of loads in a self-refresh mode in response to a failure of a primary power supply. A shared backup power supply system can also include the shared backup power supply to provide backup power to the plurality of loads in the self-refresh mode in response to the failure of the primary power supply.