Abstract: An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.

Abstract: A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Abstract: A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.

Abstract: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

Abstract: A memory system includes a controller having first and second input/output terminals, and first and second memory devices each having first and second input/output terminals. The system includes a path selection mechanism for selectively employing one of the first and second terminals of either the controller or the first memory device for communicating a first input/output signal between the controller and the first memory device, and employing the other one of the first and second terminals for communicating a second input/output signal between the controller and the first memory device. The path selection mechanism selectively employs the first and second terminals in accordance with data indicating which of the first and second terminals of the first memory device is connected to the first terminal of the controller and which of the first and second terminals of the first memory device is connected to the second terminal of the controller.

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.

Abstract: A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.

Abstract: A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.

Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.

Abstract: A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Abstract: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

Abstract: A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.

Abstract: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.

Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.

Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.

Abstract: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Abstract: A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.

Abstract: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.

Abstract: A data interface unit is used in a semiconductor memory device and includes a data alignment unit configured to separate consecutive input data into rising data and falling data, and a data transfer unit configured to selectively transfer the rising data and falling data to an even column line and an odd column line in response to a start column address.

Abstract: A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining, if the first port and the second port are simultaneously requesting to access the memory cell, the second port is deactivated, the memory cell is accessed from the first port, and an accessed memory state is propagated from the first port to circuitry associated with the second port.

Abstract: High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

Abstract: Provided is a pipeline circuit capable of flexibly controlling clock frequencies regardless of whether a pipeline operation by a flow control is stopped or not, without significantly increasing a processing latency even if a clock frequency is decreased, and in response to performance requests for a processing throughput. Among P clocks (P is a positive integer), the phases of which are delayed in the order from a first clock to a P-th clock, for example, among six clocks of P0 to P5, two successive clocks, the phases of which are delayed from each other by a predetermined phase, are allocated to a plurality of stages, for example, five-stage pipeline buffers 32a to 32e, in the order from a previous stage to a subsequent stage, and also are allocated so that one clock signal having an identical phase is shared between two adjacent pipeline buffers.

Abstract: Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

Abstract: An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.

Abstract: An output driver includes a control signal generation unit configured to generate a control signal in response to a driving strength signal and a power supply voltage level, and a driving signal generation unit configured to buffer a pre-driving signal and generate a driving signal for driving an output data, wherein a driving strength of the driving signal is adjusted in response to the control signal.

Abstract: A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode; a plurality of data transfer lines for transferring data between the matrices and the test data I/O units, wherein the data transfer lines is grouped into the number of matrices; and a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data.

Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

Abstract: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.

Abstract: A circuit apparatus includes an output circuit that outputs a signal to a host apparatus via a bus, and an output control circuit that controls the output circuit. The output circuit has a first conductive transistor provided between an output node and a first power source node, and a second conductive transistor provided between the output node and a second power source node. In a first output mode, the output control circuit controls one of the first conductive transistor and the second conductive transistor to go to off and controls the other transistor to go to on/off, whereas in a second output mode, the output control circuit controls the first conductive transistor to go to on and the second conductive transistor to go to off or vice versa.

Abstract: At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of the column without using a read amplifier.

Abstract: A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.

Abstract: A reading device for a memory array is provided. The memory array comprises memory cell columns. The reading device comprises first sensing amplifier groups, a second sensing amplifier group, and an output unit. Each first sensing amplifier groups selectively generates a first sensing output signal. The second sensing amplifier group generates a second sensing output signal. The output unit selectively outputs one of the second sensing output signal and the first sensing output signals according to a page address signal. In a reading operation period, the reading device reads data from a column group to the first sensing amplifier groups. In the reading operation period, when the page address signal indicates an initial input address, initial address data read from the specific column set corresponding to the initial input address among the column group is transmitted to the second sensing amplifier group to generate the second sensing output signal.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the selection circuits being configured to select a voltage applied to a word line from the voltages, and a transfer unit configured to transfer items of control data for selecting the voltage to the selection circuits, respectively. The transfer unit includes transfer circuits which shift an enable signal in sequence. The transfer circuits include latch circuits which hold the items of control data based on the shifted enable signal, respectively.

Abstract: Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller.

Abstract: A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing subsequent and contiguous memory locations of the page-mode capable memory device.

Abstract: A non-volatile memory device includes a plurality of input pads, a buffer configured to buffer data inputted through the plurality of the input pads in synchronization with a write enable signal, an even latch configured to store a first buffered data outputted from the buffer in response to an even write enable signal, an odd latch configured to store a second buffered data outputted from the buffer in response to an odd write enable signal, and a transfer unit configured to transfer stored data in the even latch and the odd latch to a selected bank of a plane in response to a bank selection signal.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device (200) that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit (230) to delay a drop in voltage of an input/output line, a power shutdown sensor (210) to sense power shutdown of a system, and a controller (220) to control the signal delay unit in response to whether the system is shut down.

Abstract: A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit and the test unit.

Abstract: The present invention is directed to systems and methods for improving access to non-volatile solid-state storage systems. Embodiments described herein provide a physical chunk number (PCN), or a physical page number (PPN), by which a controller can access the next available chunks (or pages) in a programming sequence optimized by concurrency. By incrementing the PCN, the controller can program consecutive chunks in the optimized programming sequence. In one embodiment, the programming sequence is determined at the time of initial configuration and the sequence seeks to synchronize data programming and data sending operations in subcomponents of the storage system to minimize contention and wait time. In one embodiment, the PCN includes an index portion to a superblock table with entries that reference specific blocks within the subcomponents in a sequence that mirrors the optimized programming sequence, and a local address portion that references a particular chunk to be programmed or read.

Abstract: Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data.