Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value.

Abstract: A multi-core/multi-package bus termination apparatus includes a first node, a location array, and a plurality of drivers. The first node receives a signal indicating whether a package upon which the processor core is disposed is internal to the bus or at a far end of the bus. The location array generates location signals indicating locations on the bus of nodes, where the locations are either an internal location or a bus end location. The drivers control how the nodes are driven. Each drivers has location-based multi-core/multi-package logic. The location-based multi-core/multi-package logic enables pull-up logic and first pull-down logic responsive to states of the first node ad the location signals.

Abstract: Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to the memory array. The control circuit may be configured to selectively prevent access to data stored within the memory array upon removal of the memory component from the electronic system. Various additional methods, devices, and systems are also provided.

Abstract: Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.

Abstract: A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0 v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0 v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0 v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed.

Abstract: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.

Abstract: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation.

Abstract: An integrated circuit comprising: a) at least one integrated voltage generator for generating a low voltage for an associated integrated load; b) an integrated voltage generator test logic connected to the voltage generator which in a test operating mode which is the operating state of that integrated voltage generator between an active operating state and a standby operating state depending on an external control signal; c) an internal load switch for switching said generated load voltage to that integrated load said internal load switch being controllable by means of an internal control signal; d) wherein said voltage generator test logic in said test operating mode switches the operating state of said integrated voltage generator independently of the associated internal control switching signal for setting a temporal voltage profile of said load voltage applied to that load.

Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: For improving performance of mask ROM, bit line is multi-divided for reducing capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives an output from a memory cell through the bit line, and a global sense amp receives the local sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating data “1” and data “0”. For example, data “1” is quickly transferred to an output latch circuit through the sense amps with high gain, but data “0” is rejected by a locking signal based on data “1” as a reference signal. Furthermore, a buffered data path is used for transferring data wherein the buffered data path includes a forwarding write line and a returning read line. Additionally, alternative circuits and memory cell structures for implementing the mask ROM are described.

Abstract: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation.

Abstract: A device for protecting data stored in a static random access memory (SRAM) is provided. More particularly, a device for protecting SRAM data including an SRAM data erasing circuit, which erases memory stored in an SRAM at once when illegal separation from a system is detected. The device for protecting SRAM data includes: a power switching circuit for outputting electrical power supplied from an external power supply or a back-up battery power supply depending on whether the external power supply is supplying the electrical power or not; and an SRAM data erasing circuit for supplying the electrical power output from the power switching circuit to a power input terminal of a SRAM or grounding the power input terminal of the SRAM, in response to a connecter connection signal. The device can prevent illegal leakage of SRAM data by erasing the data stored in the SRAM when the SRAM is illegally separated from a system according to the switch setting of the SRAM data erasing circuit.

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract: An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.

Abstract: A method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit provides improved resistance to code copying and reverse-engineering attacks. External interfaces that provide read access to the NV storage are be disabled, for a predetermined time after a reset or other initialization signal is received. An internal lock state bit or key is checked as well as an external lock prevent indication. If the lock prevent indication is not received, or the internal lock state bit is already set, then the integrated circuit is operated under a locked condition, in which external access to the NV storage values is prevented. The lock prevent indication may be a signal provided during reset of the integrated circuit on a terminal that is used for another purpose after initialization of the integrated circuit.

Abstract: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

Abstract: A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed pulse signal output from the delay circuit in a test mode and the pulse signal in a normal mode.

Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: To make it possible to reliably halt writing processing while restraining erroneous writing to the memory unit, present apparatus has a memory unit to which data is written for each write request; a voltage converting unit which converts a first power source voltage into a first operable voltage with which a write request issuing unit is operable, and supplies the first operable voltage to the write request issuing unit; a voltage monitoring unit, which outputs an issuance restraining signal which restrains issuance of the write request, when the first power source voltage becomes lower than a reference voltage; and an issuance restrain controlling unit which receives the issuance restrain signal, and then after completion of writing for each of the write request to write memory unit, which restrains the issuance of the write request by the write request issuance unit.

Abstract: A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

Abstract: A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.

Abstract: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

Abstract: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level.

Abstract: A power supply control circuit and a control method secure an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal.

Abstract: A fixing device fixes a toner image on a recording medium. The fixing device includes a heat source that converts electric power into heat and a fixing member that gives the heat generated by the heat source to the recording medium on which the toner image is formed. The fixing device includes a safety circuit that forcibly interrupts voltage supplied from a power supply to the heat source if the temperature in the device detected by a temperature detection sensor exceeds reference temperature. The fixing device has a malfunction preventing circuit that stops the operation of the safety circuit in order to prevent the voltage supplied to the heat source from being forcibly interrupted when the voltage of the power supply supplied to the heat source is unstable.

Abstract: A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

Abstract: An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit generates the control signal at the second level in ‘no operation’ state (NOP command) in which the semiconductor memory device does not perform data accessing operations and generates the control signal at the first level while the semiconductor memory device performs data accessing operations, thereby reducing or minimizing the output of an internal address buffered and output by the address buffer at and thus reducing power consumption during no-operation states of the semiconductor memory device.

Abstract: A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.

Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

Abstract: A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus, comprising a control terminal, and a level shifter, shifting a voltage level of an enabling signal to a first power voltage from a second power voltage lower than the external programming voltage. When the second power voltage is not ready during power up, the level shifter sets the control terminal of the switching unit to a predetermined logic level such that the switching unit is turned off and the source bus is disconnected from the external programming voltage thereby preventing false programming.

Abstract: A semiconductor memory device checks a RAS timing to recognize and set an operation timing of the semiconductor memory device. The semiconductor memory device includes an input buffer, a RAS timing controller and a bank controller. The input buffer transmits a RAS timing test signal. The RAS timing controller generates a RAS timing signal. The bank controller controls a refresh operation timing in response to an output of the input buffer in a test mode and the RAS timing signal in a normal mode.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.

Abstract: Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

Abstract: A method and apparatus for write enable and write inhibit for high density spin torque three dimensional (3D) memory arrays.

Abstract: A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines and a main bit line in an activated memory array to be connected all the time. With this configuration, it is possible to perform a disturb refresh test on a memory cell arrays basis regardless of the hierarchical bit line structure. Possibility of an erroneous read-out, which may be caused by connecting each of the hierarchical bit lines to one another and a consequent increase in a bit line load capacity, may be prevented by providing a timing control such that the switches are connected after a normal mode operation.

Abstract: Disclosed are a method and device for programming an array of memory cells.

Abstract: A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded together. According to one embodiment, the plurality of network units comprise a plurality of content based message directors, each to route or direct received messages to one of a plurality of application servers based upon the application data in the message. According to another embodiment, the plurality of network units comprise a plurality of validation accelerators, each validation accelerator to validate at least a portion of a message before outputting the message.

Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.

Abstract: A programmable processor and methods thereof are provided. The example programmable processor may include a memory lock signal generator outputting a memory lock signal, the memory lock signal indicating whether a requesting entity has authority to access requested data stored in a memory and a memory access controller receiving a request for the requested data and the memory lock signal, the memory access controller outputting a response to the requesting entity in response to the request based on the memory lock signal. A first example method may include receiving a request, from a requesting entity, to access requested data stored in a memory, determining information associated with the requesting entity and selectively outputting a response to the received request based on a security level of a location of the requested data within the memory and the determined information.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it looses its power connection to the host system.

Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.