Abstract: An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Abstract: A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

Abstract: A multiple power supply connection memory that prohibits initialization until each power supply connection is powered up. Requiring all power supply connections to be powered up before initialization greatly increases the reliability of the memory. In one embodiment, low sense circuits are coupled to each power supply connection to monitor voltage levels. The memory can prohibit initialization and/or prohibit access operations until each power supply connection has an appropriate voltage level.

Abstract: The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

Abstract: There is provided an inventive semiconductor memory device and control method thereof capable of preventing shift operation to deactivated state and data access due to transition of address signals from occurring concurrently without accompanying delay of access time, thereby to prevent data-holding characteristic of memory cell from deteriorating. A column selecting circuit 16 is deactivated based on an input signal EXBn outputted to a glitch canceller 20 prior to precharge signal PRE so as to prevent selection of a column selecting signal CLn and deactivation of a word line WL from occurring concurrently. This manner substitutes for taking delay time &tgr;D that is to be added to signals CAGn from which glitch noises due to transition of address CAn are eliminated.

Abstract: A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Abstract: A method and system masking data being written to a memory device having a data bus. One method includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.

Abstract: A nonvolatile semiconductor memory device includes a plurality of banks including respective memory cell arrays independent of each other, a password storage area that is associated with one of the banks, a bank decoder which generates a bank selection signal by decoding a bank address, a first bank selection circuit which outputs a write instruction or a read instruction to the one of the banks, a plurality of second bank selection circuits which outputs a write instruction or a read instruction to the respective banks except for the one of the banks, and a command-decode-&-bank-control circuit which controls the first and second bank selection circuits such that receipt of a first command causes one of the first and second bank selection circuits selected by the bank selection signal to output a write instruction or a read instruction, and such that receipt of a second command causes the first bank selection circuit to output a write instruction independently of the bank selection signal, and causes one

Abstract: An apparatus and method for controlling a refresh operation of a memory device capable of performing an internal refresh after a power-up sequence is completed. The apparatus an apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprises a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

Abstract: A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an input and an output to each external functional block in accordance with the logical content of the memory, wherein a user is allowed to validate use of a necessary external functional block and to invalidate use of an unnecessary external functional block.

Abstract: A semiconductor memory device of the present invention includes: a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.

Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., x16 or x32.

Abstract: A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

Abstract: An integrated circuit for processing security-relevant data has data output circuits and access control circuits wherein a disturbance of the power supply of the access control circuits results in a blocking of the data output circuits.

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Abstract: A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

Abstract: A split-gate flash memory array is programmed, in part, by applying a programming voltage to the row of cells that include the to-be-programmed cells, and an inhibiting voltage to the row of cells that share the same source line as the row that includes the to-be-programmed cells. The inhibiting voltage is greater than zero and less than the programming voltage.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: A system and method of storing data using write once read many (WORM) protection including using a hardware storage device to write data to a medium are provided. The method further includes establishing a write once read many (WORM) module external to the hardware storage device. Data blocks are received at the module, block numbers are specified with the module, and data is output from the module to write to the storage medium at specified block numbers. The last specified block number or all specified block numbers depending on the type of media access are stored so that the external WORM module prevents future writing of data to these specified or already used block numbers.

Abstract: A method and system masking data being written to a memory device having a data bus. One method includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an input and an output to each external functional block in accordance with the logical content of the memory, wherein a user is allowed to validate use of a necessary external functional block and to invalidate use of an unnecessary external functional block.

Abstract: Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.

Abstract: Chip area and operating current is reduced in a chip having a write-inhibit circuit that uses a data-writing request signal WR and a write-control signal WRITE to inhibit data writing. By comparing a reference current Iref and a drive current ID, a current-mirror circuit CM can monitor the voltage of a power supply VDD. When the voltage of the power supply VDD is sufficiently high, the data-writing request signal WR is unchanged. Conversely, when the voltage of the power supply VDD is not sufficiently high, a transistor T6 producing reference-current ID and a buffer B2 cause the write-control signal to be low “L” irrespective of whether the data-writing request signal WR is at “H” or at “L”. Thus, miswriting can be prevented when the power-supply voltage decreases, since writing by the data-writing request signal WR is impossible.

Abstract: A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signal. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.

Abstract: A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices.

Abstract: A semiconductor integrated circuit includes a first address transition detecting circuit which detects transitions of a row address signal and a column address signal of a memory cell array, a second address transition detecting circuit which detects only the transition of the column address signal, a control circuit which generates an internal circuit control signal with a desired period of time required for row access based on only a first detection signal and generates a column-related circuit control signal with a desired period of time required for column access to the memory cell array based on only a second detection signal, and a mode discriminator which determines one of the row access and the column access to be made and performs the access control operation based on the determination result.

Abstract: A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.

Abstract: A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage Vpp from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.

Abstract: A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.

Abstract: A write-protected memory device has two write modes. Such memory device has many memory cells organized into pages. A normal write mode checks a one-bit flag collocated with every memory cell to see if writes are allowed. If the flag indicates a write operation to that memory cell is allowed, the flag is toggled and the cell is written. If the flag has previously been toggled, the write operation is prevented. A special write mode allows write operations to memory cells regardless of the state of the one-bit flag. The special write mode can be discerned in hardware by the loading of a register with a reprogrammable password, or the splitting of a normal single write-enable pin into two independent pins, e.g., normal write and special write.

Abstract: A memory system including an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level.

Abstract: A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic circuits that begin operation from an initial condition after the application of the power supply voltage and an input signal. In one embodiment, a dynamic random access memory (DRAM) of the present invention begins operation after receiving an address strobe signal. The address strobe signal is coupled to the power up pulse generator circuit to assure that the power up pulse is of sufficient duration to reset internal registers and so establish the initial condition. The power up pulse generator circuit of such an embodiment includes a selectively enabled input buffer, a selectively enabled one shot, and a flip flop designed to assume a predetermined state on application of the power supply voltage.

Abstract: A signal delay circuit (100) is provided for inhibiting an output control signal (/OE), which is externally input, from transferring to an output buffer (6) for a predetermined period after an address changes. While a sense amplifier (1) senses data in the predetermined period after the address changes, the logic level of a signal (OUT) output from the output buffer (6) is inhibited from being inverted. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier (1).

Abstract: A semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory while sharing a data bus, and utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. This volatile memory includes a volatile storage circuit for latching repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. A fuse program circuit is not needed for the defect repair, but a defect which occurs after burn-in can be newly repaired so that the new defect can be repaired even after the packaging is formed over a circuit substrate.

Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.

Abstract: In a multiple bits product, when respective bit is in a specific data direction, a selecting signal for making a corresponding column selecting switch ON is made ineffective. Thereby, in the multiple bits product, whether writing is executed in an arbitrary data direction can be selected for respective bit.

Abstract: In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.

Abstract: A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.

Abstract: An integrated circuit is disclosed which includes a start test mode circuit for generating a test mode start-up signal to cause the integrated circuit to enter a test mode, and an automatic reset circuit responsive to the test mode start-up signal for preventing the integrated circuit from erroneously entering a test mode during normal operation.

Abstract: A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

Abstract: A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).

Abstract: A method of accessing a semiconductor memory comprising ferroelectric memory FETs arranged as a matrix to allow write and/or read data to and from only an intended memory cell without the data in not-intended cells being destroyed by the application of a disturbing voltage to not-intended cells, even without providing each cell with a selection element. The method is characterized in that, when data are written to or read from memory cells Q1 through Q4 arranged as a matrix comprising ferroelectric memory FETs each having a ferroelectric layer on the gate side to constitute a semiconductor memory, a voltage of a direction opposite that of the voltage for writing or reading the data is applied, followed by the application of a voltage for writing or reading.

Abstract: A method of protecting a microcomputer system against manipulation of its program, in which the microcomputer system includes a rewritable memory in which at least one portion of the program is stored, and in which a check is performed as part of a checking procedure to determine whether at least one portion of the rewritable memory includes a specified content. To permit detection of a manipulated program in the shortest amount of time, the checking procedure is executed cyclically at preselectable intervals during operation of the microcomputer system. In addition, execution of the program is blocked immediately as part of the checking procedure if the rewritable memory or a portion thereof does not include the specified content.

Abstract: In the semiconductor memory device of the present invention, a page buffer holds read data read from a memory cell selected from among a plurality of memory cell blocks, and outputs the held data in order. That is, read data is read not directly from the memory cell blocks but through the page buffer. A password control circuit compares a read password supplied during a read operation with an original password stored in advance, and outputs the result of comparison. A buffer control circuit changes the order the read data is output from the page buffer when the result of comparison is a mismatch. In other words, the page buffer outputs the read data in predetermined order when the read password is correct, and outputs the read data in random order when the read password is incorrect. This realizes security protection of the data written in the semiconductor memory device.

Abstract: It is determined whether one or more memory devices coupled with each output of one or more output buffers by a terminated bus are in a first power state or a second power state. Each output buffer has a first impedance state and a second impedance state. The one or more output buffers are placed or maintained in the first impedance state in response to determining each of the one or more memory devices is in the first power state.

Abstract: An asymmetrical switching element including a random access memory element, a first port selectively coupled to the memory element by first control signal and a plurality of second ports, each independently coupled to the memory element by corresponding one of a plurality of second control signals.