Abstract: A memory testing method and apparatus each capable of performing an erase test for a non-volatile memory in a short time are provided. In case of carrying out an erase test inspecting as to whether the storage data in each of the memory cells in a block to be tested of a non-volatile memory has been erased or not by an erasing operation, there are provided two failure address storage memories each storing therein addresses of failure memory cells. These failure address storage memories are alternately used to store therein only addresses of failure memory cells detected during the erase test. In the second time and the succeeding erase tests, the addresses of the failure memory cells stored in either one of the failure address storage memories in the preceding erase test are read out to access only the failure memory cells in the memory under test, thereby to inspect as to whether the storage data in each of the failure memory cells has been erased or not.

Abstract: A memory device having a plurality of data paths connected between a main memory by a plurality of data pads. Each of the data path transfers a first and second data bits from the main memory to a data pad in one clock cycle during a read operation. The first data bit is transferred to the data pad in a shorter path than the path of the second data bit.

Abstract: A memory diagnostic circuit includes: a diagnostic circuit which sets a plurality of memory banks to an access/enable state at one time, writes predetermined common data into the memory banks, and parallelly reads out storage data of the plurality of memory banks; a comparison circuit which compares the data read out from the plurality of memory banks with the data written into the memory banks; and a discrimination circuit which discriminates whether or not there is any defect in the plurality of memory banks based on a comparison result.

Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is preempted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.

Abstract: According to the present invention, access to a password area in a nonvolatile memory cannot be granted by simple supply of an address in a normal order. According to one preferable mode, for instance, a trap address is set in the password area so that reading information from the password area is permitted only when the password area is accessed without accessing the trap address, whereas when the password area is accessed the trap address, whereas when the password area is access through the trap address, information reading is inhibited, or meaningless data is output or the information in the password area is destroyed. This invention can make it harder to gain access to a password area which is used to protect against illegitimate copying and can provide a nonvolatile memory having a stronger copy protection capability.

Abstract: A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference voltage, the enable control circuit drives the enable input to place the CAM into a low current, stand-by mode of operation. A voltage supply back-up circuit is connected to the voltage power supply input, and operates to compare the external voltage to a supply reference voltage. If the external voltage drops below the supply reference voltage, the voltage supply back-up circuit switches the voltage power supply input for the CAM from the external voltage input to a battery back-up. As an alternative, the voltage power supply input for the CAM includes a separate power input for a CAM array, and the switch causes only that separate power input for the CAM array to be powered from the battery back-up.

Abstract: A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: A memory controller portion of a DRAM is synchronized to a system clock, while an array portion of the DRAM is allowed to process signals at the array's natural frequency—independent of fixed timing parameters. By allowing the array portion to function at its natural frequency, the array's performance is not limited to “worst case” parameters; instead the DRAM can achieve maximize array performance at all voltage and temperature corners. The controller portion of the DRAM initiates an array access cycle, then waits until the array portion returns a data-valid signal. Since the array portion of the DRAM operates at its own natural frequency the data-valid signal can be completely asynchronous to the controller portion of the DRAM, which is operating in synchronization with a system clock. In order to ensure that the data-valid signal is latched properly, the controller sends an early version of the system clock to the data valid circuitry in the array portion of the DRAM.

Abstract: A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation.

Abstract: An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

Abstract: A method of controlling the operation of a memory system includes monitoring the magnitude of a programming voltage, and initiating a memory programming operation only in the event that both a memory program command is detected and the programming voltage falls within a first or a second voltage range. The first voltage range has a lower limit, the second voltage range has an upper limit, and the lower limit is of greater magnitude than the upper limit. Alternatively, a method of controlling the operation of a memory circuit includes detecting a programming voltage, comparing the programming voltage to multiple acceptable voltage ranges, and initiating a memory program command if the programming voltage is acceptable.

Abstract: A method for controlling an input circuit of a synchronous semiconductor memory device that reduces current consumption without changing commands or increasing signal input terminals. The synchronous semiconductor memory device includes an input circuit for receiving write data and is operated based on a synchronizing signal. When the synchronous semiconductor memory device is active, the input circuit is selectively inactivated based on a mask control signal, which masks the write data. When the synchronous semiconductor memory device enters a write mode in which the synchronous semiconductor memory device stores data, the input circuit is activated and the mask control signal is invalidated.

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

Abstract: An apparatus and method for protecting memory blocks in a block-based flash erasable programmable read only memory device are disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register is coupled to each of the lockable blocks in the memory array. A logic state is coupled to one input of the volatile lock register, and a block set/reset line is coupled to a second input of the volatile lock register. A block latch control line is coupled to one input of the logic gate, and a group latch control line is coupled to a second input of the logic gate. The method includes reading a first command of a multi-cycle command specifying a lock configuration of one or more memory blocks and reading a second command specifying the number of memory blocks to be lock configured.

Abstract: An electronic device that invalidates a memory write operation before a memory address predecode occurs. The electronic device uses several dynamic latches to assert complementary clock like memory address data to drive the associated predecode circuitry. A stack of serially connected transistors is coupled to the input node of each dynamic latch to provide input node state control. By managing the operation of each stack of serially connected transistors, the dynamic latches may be prevented from asserting their complementary clock like memory address data to the associated predecode circuitry in order to invalidate a memory write operation.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Abstract: The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

Abstract: A method is provided to prevent flash memory in a computer system from being miswritten. According to this method, a control parameter records the normal paths of a process module. Then a judge module decides whether or not the flash memory is to be written. When the judge module decides the flash memory is to be written, a prepare module conducts preparations for the flash memory. Then a check module is provided to confirm the normal paths from the process module in response to the control parameter, and a write module is provided to write the flash memory when the check module confirms the normal paths from the process module. An error module may be provided to restart the process module or the computer system or provide a warning signal when the check module does not confirm the normal paths from the process module.

Abstract: A mechanism is provided for self timing a memory circuit to compensate for sense amplifier imbalance. The self timing mechanism comprises two self timed sense amplifiers. A first self timed sense amplifier reads a first state and a second self timed sense amplifier reads a second state. The control logic deactivates the real sense amplifiers in response to the slower of the two self timed sense amplifiers. Thus, even if there is a layout or processing variance, which causes the sense amplifiers to have a non-zero offset voltage and favor a certain output state when the inputs are equal, the real sense amplifiers are able to read the states of the memory cell.

Abstract: An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Abstract: An enhanced compact micro memory card with write protection, comprises an enclosed casing, and a switch circuit of data write protection. The enclosed casing provides a micro controller and a plurality of memories therein, and has a connector for external connection. The switch circuit of data write protection provides a micro switch and the micro switch exposing outward the casing for switching an operation of write protection.

Abstract: A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an input and an output to each external functional block in accordance with the logical content of the memory, wherein a user is allowed to validate use of a necessary external functional block and to invalidate use of an unnecessary external functional block.

Abstract: Output driver stages and operation modes for selectively disabling device outputs are adapted for use in integrated circuit devices and in the testing of such integrated circuit devices. A device output is disabled by disabling its associated output driver. A first control signal is generated that is indicative of whether an output driver should be responsive to a second control signal or disabled regardless of the second control signal. The first control signal may be provided directly to one or more output drivers. Alternatively, the first control signal may be combined with the second control signal. The first control signal may be common to all coupled output drivers or a separate first control signal may be provided for each output driver. Selective disabling of output drivers can be used to force a device time-out during testing. Selective disabling of output drivers can also be used to reduce device power requirements.

Abstract: A write-once memory device includes a memory array controller and an electronically resetable flag. The memory array controller prevents writing and erasing from a write-once memory array unless the flag is in a selected state. The memory device is used with a data storage system that automatically determines whether a memory device installed in the data storage system is a write-once memory, and then automatically sends a recognition signal to the memory device once it has been determined to be a write-once memory. The memory device (1) automatically sets the flag in response to the recognition signal, (2) automatically refuses to implement write and erase commands prior to receipt of the recognition signal and setting of the flag, and (3) implements write and erase commands subsequent to receipt of the recognition signal and setting of the flag. The memory device implements nondestructive commands such as read and status commands regardless of the state of the flag.

Abstract: A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Abstract: A method for testing a multi-level memory includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. The method further includes during a first test phase operating the multi-level memory at the initial values of the plurality of performance variables and reading program values of the plurality of performance variables. During a second test phase, the multi-level memory is operated at the program values of the plurality of performance variables.

Abstract: The present invention is provided with a switch circuit which can turn on/off electric power supply from a battery. Further, a CPU transfers and evacuates specific data stored in a DRAM when electric power supply from a main power supply is stopped and electric power supply from a battery is performed. Thereafter, the CPU turns off the switch circuit and stops electric power supply from the battery.

Abstract: In a multiple bits product, when respective bit is in a specific data direction, a selecting signal for making a corresponding column selecting switch ON is made ineffective. Thereby, in the multiple bits product, whether writing is executed in an arbitrary data direction can be selected for respective bit.

Abstract: Column select gates are provided to normal bit lines and refresh bit lines, respectively. When a refresh request and a data access instruction are applied on the same row, it is determined which of refresh and data access is instructed earlier, and one of a normal bit line pair and a refresh bit line pair is connected to an internal data line pair according to the determination result. A semiconductor memory device is provided by which access time is not increased even when refresh and ordinary access conflict with each other.

Abstract: Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a plurality of memory elements selected by an address signal. The second storage area has a plurality of memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A semiconductor memory device is provided which includes a rewrite-inhibited region for individual certification. Non-volatile memory elements constituting a memory cell array are used instead of a conventionally used fuse element to form the rewrite-inhibited region for individual certification. A voltage at high level is applied to a pad formed on a chip with a probe before the chip is sealed in a package to set the non-volatile memory elements in the rewrite-inhibited region to a writable state. After data for individual certification is written thereto, the chip is sealed in a package to disable electrical connection from outside to the pad set to a voltage at low level with a pull-down resistor.

Abstract: A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic circuits that begin operation from an initial condition after the application of the power supply voltage and an input signal. In one embodiment, a dynamic random access memory (DRAM) of the present invention begins operation after receiving an address strobe signal. The address strobe signal is coupled to the power up pulse generator circuit to assure that the power up pulse is of sufficient duration to reset internal registers and so establish the initial condition. The power up pulse generator circuit of such an embodiment includes a selectively enabled input buffer, a is selectively enabled one shot, and a flip flop designed to assume a predetermined state on application of the power supply voltage.

Abstract: An integrated circuit chip responds to clock waves having differing frequencies at different times. The chip includes a semiconductor memory cell having a write enable input terminal responsive to a write enable signal having first and second levels. The cell has a tendency to operate improperly in response to the first level of the write enable signal having an excessively long predetermined duration. A write enable signal source responds to the clock waves so that for clock waves having half cycles of duration less than the predetermined duration the first level of the write enable signal has durations approximately equal to the durations of the half cycles of these clock waves. For clock waves having half cycles of duration greater than the predetermined duration, the first level of the write enable signal has a duration substantially equal to the predetermined duration.

Abstract: A memory circuit is described which includes distributed voltage generators to selectively provide power to memory arrays of the memory circuit. Each memory array can be turned off by deactivating its voltage generator if it is determined that the memory array is defective and cannot be repaired. The memory device, therefore, can be salvaged by reducing the operational capacity of the memory device. The distributed voltage generators can be selectively deactivated to test the memory circuit.

Abstract: In order to provide a more efficient method and system for data lookups, it is proposed to provide the known CAM (100) with an additional comparator (301). The comparator (301) does not comprise a memory circuit and therefore allows a faster comparison of input data (D0 to D31) with compare data (C0 to C31) than the known compare circuit (106). In addition, it is proposed to temporarily inhibit forwarding of the output signal of the specific CAM circuit into which the input data (D0 to D31) are written, in order to avoid forwarding of a wrong match signal to the data processing system.

Abstract: A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

Abstract: An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

Abstract: For a semiconductor memory device having a global data bus, a memory array and internal data write circuitry between the bus and array. The internal data write circuitry has a data mask current that inhibits writing of data into selected memory cells in accordance with a data mask designating signal.

Abstract: A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as /CS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.

Abstract: A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes.

Abstract: A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among a plurality of memory cells in the memory cell array, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A semiconductor memory device includes word lines, normal bit lines, a redundant bit line, and normal memory cells for storing data and each of which is coupled to one of the word lines and to one of the normal bit lines. The device also includes redundant memory cells each of which is coupled to one of the word lines and to the redundant bit line. The device further includes a coincidence circuit that receives a first address signal, indicating an address of one of the normal bit lines, and a second address signal, indicating an address of one of the normal bit lines to which a defective memory cell is coupled, and which selects the redundant bit line when the first address signal coincides with the second address signal.

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract: To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a dat bus (16), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes volatile storage circuit (12AR, 13AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory.

Abstract: A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.

Abstract: A multi-level memory includes an array of memory cells accessible through respective word lines and bit lines a control circuit controlling embedded operations of the memory and a read voltage generating circuit to generate a descending staircase read voltage to a word line associated with a selected memory cell under control of the control circuit. The multi-level memory further includes a read circuit including a latch circuit, and a switch circuit responsive to an evaluate/enable signal to selectively store a read state signal in the latch circuit in response to a sense signal generated from application of the descending staircase read voltage to the word line associated with the selected memory cell.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.