Abstract: A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. The sense amplifier reads data according to a difference between the first current and the second current.

Abstract: A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.

Abstract: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: Transistors formed in one identical diffusion layer and performing complementary operations are generally arranged symmetrically with respect to the diffusion layer. A semiconductor integrated device using a layout capable of partially avoiding restriction on the design of the semiconductor integrated circuit device and reducing the size and economizing the manufacturing cost is provided by breaking the stereotype idea. The size of the semiconductor integrated circuit device can be decreased further by arranging two transistors formed in one identical diffusion layer and conducting complementary operations by intentionally arranging them in an asymmetric pattern.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: A memory system includes a controller having first and second input/output terminals, and first and second memory devices each having first and second input/output terminals. The system includes a path selection mechanism for selectively employing one of the first and second terminals of either the controller or the first memory device for communicating a first input/output signal between the controller and the first memory device, and employing the other one of the first and second terminals for communicating a second input/output signal between the controller and the first memory device. The path selection mechanism selectively employs the first and second terminals in accordance with data indicating which of the first and second terminals of the first memory device is connected to the first terminal of the controller and which of the first and second terminals of the first memory device is connected to the second terminal of the controller.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive effect element including a first magnetic layer invariable in magnetization direction, a second magnetic layer variable in magnetization direction, and an intermediate layer between the first magnetic layer and the second magnetic layer, an error detecting and correcting circuit which detects whether first data in the magnetoresistive effect element includes any error and which outputs error-corrected second data when the first data includes an error, a writing circuit which generates one of the first write current including a first pulse width and the second write current including a second pulse width greater than the first pulse width, and a control circuit which controls the writing circuit to pass the second write current through the magnetoresistive effect element when the second data is written into the magnetoresistive effect element.

Abstract: A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a first bit line (754) extending in a first direction and a second bit line (752) extending in a second direction parallel to the first bit line. A second sense amplifier (704) has a third bit line (756) adjacent and parallel to the first bit line. The third bit line remains inactive while the first bit line is active.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

Abstract: A stream data reproducing system comprising: an input buffer configured to accumulate stream data input from a stream source; a decode circuit configured to decode the stream data accumulated in the input buffer by predetermined processing unit to generate decode data; an output buffer configured to output the decode data after accumulation thereof; a transfer memory cell configured to store the stream data accumulated in the input buffer and the decode data generated in the decode core circuit; and a data transfer control circuit configured to control transfer of the stream data by the processing unit from the input buffer to the transfer memory cell, and transfer of the decode data by the processing unit from the transfer memory cell to the output buffer.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract: Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

Abstract: A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.

Abstract: A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in the well, is distanced from a boundary and are disposed in the center region of the well, while non-sensitive element is disposed in the peripheral region close to the boundary in the well. Since sensitive element requiring precise control of threshold voltage is disposed in the center region having uniform impurity density, and non-sensitive element allowing for less precise control of threshold voltage is disposed in the peripheral region suffering from uneven impurity density, it is possible to effectively use the overall area of the well and to thereby suppress an increase in the layout area of chips.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract: A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the node supplies the reference voltage. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source.

Abstract: A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bit line direction. The cell array includes first P-well regions and first N-well regions shaped in stripes extending in the bit line direction and arranged alternately in the word line direction. The SRAM cell is formed point-symmetrically in the first P-well region and the first N-well regions located on both sides thereof. The peripheral circuit includes second P-well regions and second N-well regions extending in the bit line direction and arranged alternately in the word line direction.

Abstract: Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract: A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.

Abstract: A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the bit line. An equalizing transistor is disposed between the gate electrode of the first transistor and the gate electrode of the second transistor. The first electrode of the first transistor and a first electrode of the equalizing transistor are electrically connected to each other, and the first electrode of the second transistor and a second electrode of the equalizing transistor are electrically connected to each other.

Abstract: Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

Abstract: A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.

Abstract: A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, and a second non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. The first magnetic layer, the second magnetic layer and the third magnetic layer are coupled such that spontaneous magnetizations have a helical structure.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit.

Abstract: A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. A gate of the first selecting transistor is connected to the 2·N?1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: A semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying unit coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying unit in response to a control signal.

Abstract: A semiconductor memory device includes first and second column selection signal lines, first bit lines being and second bit lines. The first bit lines are associated with the first column selection signal line. The second bit lines are associated with the second column lines. At least one of the first bit lines is positioned between two of the second bit lines.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

Abstract: Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.

Abstract: Radiation hardening, detection and protection design methods are disclosed. An example write drive circuit is disclosed having radiation hardened analog circuitry. A passive transistor is provided to generate a radiation photo-current to offset any net radiation photo-current of the operational circuitry. Using this technique, a radiation hardened reference-mirror control circuit provides a switched write current for setting the logical state of MRAM bits during a radiation event, for instance. A radiation detector and radiation hardened logic gates are further provided for inhibiting the write current when a radiation level is above a predetermined level.

Abstract: Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.