Abstract: A semiconductor device includes a first region having first bit lines, first word lines and first memory cells; a second region having second bit lines, second word lines and second memory cells; a third region having sense amplifiers placed between the first region and the second region; a first conductive layer being over the first region; a second conductive layer being over the second region; and a connecting layer, being over the third region, which electrically connects the first conductive layer with the second conductive layer. The sense amplifiers amplify differences in voltage between the first bit lines and the second bit lines. Each of the first memory cells includes a first storage capacitor having an electrode connected to the first conductive layer. Each of the second memory cells includes a second storage capacitor having an electrode connected to the second conductive layer.

Abstract: A magnetoresistve memory device includes a magnetoresistive element and a wiring for applying a magnetic field to the magnetoresistive element. The wiring includes two or more conductive wires that extend in the same direction. A plurality of conductive wires is used to apply a magnetic field to a single magnetoresistive element, thereby achieving high-speed response and suppressing crosstalk.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: The invention discloses a semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops. In order to maintain constant the array voltage used for a single memory cell array region the plurality of feedback loops dividedly connect to a power line structure covering the memory cell array region, resulting in a reduction in the load to be taken by the output of feedback amplifiers to thereby achieve stable array voltage control operations.

Abstract: A method for driving a semiconductor memory including a field effect transistor having a gate electrode formed on a ferroelectric film includes the steps of writing a data in the semiconductor memory by changing a polarized state of the ferroelectric film by applying a voltage to the gate electrode, and reading a data written in the semiconductor memory by detecting a current change appearing between a drain and a source of the field effect transistor by applying a voltage between the drain and the source of the field effect transistor with a voltage applied to the gate electrode. The magnitude of the voltage applied between the drain and the source of the field effect transistor in the step of reading a data is set within a range where a drain-source current of the field effect transistor increases as a drain-source voltage thereof increases.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208t) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208t) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.

Abstract: A data memory for storing data, having a memory cell array (2), which comprises a large number of memory cells (3), each of which can be addressed by means of a memory cell select transistor (4) connected to a word line (9) and to a bit line (13) and which have a storage capacity for storing one data bit, the memory cell array (2) containing redundant memory cells (3′), which are provided in order to replace memory cells (3) which have been produced wrongly, by means of readdressing, and having read amplifiers (22), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell (3) via an associated bit line (13) and are supplied with a buffered supply voltage, the redundant memory cells (3′) which have not been readdressed being connected to the associated bit lines (13′) and additionally buffering the supply voltage for the read amplifiers (22).

Abstract: A content addressable memory (CAM) device according to the present invention is configured with binary CAM cells capable of holding binary data “0” and “1”, and is capable of being used either as a binary CAM device with the binary CAM cells being used as binary CAM cells or as a ternary CAM device with the binary CAM cells being used as ternary CAM cells capable of holding ternary data in a way in which, in each pair of two bits of the binary CAM cells, three states, “0,” “1,” and “X (don't care)” are assigned to four states, “00,” “01,” “10,” and “11,” expressed by two-bit data stored in the pair.

Abstract: A test array includes row conductors, column conductors, and memory cells located at crossing points of the row and column conductors. The test array can have groups of the row conductors or the column conductors electrically coupled, or ganged together, so that they share common terminals. Other selected row and column conductors can have individual terminals. In this configuration, memory cells located at the intersection of row and column conductors that have individual terminals can have their characteristics measured using a test apparatus. Ganging together groups of row or column conductors means that the test array has fewer terminals for connection to the test apparatus. Therefore, a test apparatus having a limited number of probes for connection to test array terminals can be used to test arrays of various sizes.

Abstract: A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold leakage current.

Abstract: A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Abstract: Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. The method includes forming a first layer of insulating material on the first layer of the electrically conductive material. The first layer has a thickness of less than 1.0 micrometers (&mgr;m). A transmission line is formed on the first layer of insulating material. The transmission line has a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is formed on the transmission line.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are positioned with respect to the memory array (411) such that the write path length along conductive lines of the MRAM device (401) is substantially the same for all memory cells in the array (411), ensuring that the resistance along the write path is substantially uniform, and therefore, the amount of write current provided by the CVC circuits to write the cells of the memory array (411) is substantially the same.

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

Abstract: In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanced capacitance resulting from a size difference of n-FET and p-FET latches in the sense amplifiers. An extra compensating capacitance Ce is added to the NCS node to adjust the loading capacitance to eliminate the bitline drifting.

Abstract: A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

Abstract: A method for reducing electrical coupling within a computer multi-port memory cell array is provided. The method comprises twisting complementary wires of a first, inner bit line pair in a first memory cell column, wherein the twisting reverses the complementary wires, and wherein the physical twisting occurs in odd numbered dummy rows, twice along a column. The complementary wires of a second, outer bit line pair in the same column, wherein the physical twisting occurs in even numbered dummy rows, once along the column. The complementary wires of a third, inner bit line pair in a second memory cell column are then twisted, wherein the physical twisting occurs in even numbered dummy rows, once along the column, and the complementary wires of a fourth, outer bit line pair in the second column are twisted in odd numbered dummy rows, twice along the column.

Abstract: A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Abstract: A semiconductor memory device is provided which enables faults in a word line to be redressed with almost no increase in chip size and which does not cause layout problems even in advanced miniaturization. A driver simultaneously drives four word lines. A memory cell connected to these word lines is selected by a selection transistor. Using wiring for connecting word lines, two adjacent word lines are connected at the far end as seen from the driver to form a loop. If a fault occurs at a location on a word line, the driver supplies a charge to the word line from the far end thereof to the fault location via the above wiring and the other word line. Therefore, the word potential at the far end past the fault location is at or above a memory cell threshold voltage, and the memory cell can be read correctly.

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract: There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.

Abstract: A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.

Abstract: A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an “open” configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another.

Abstract: A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level.

Abstract: Main word lines are shifted in the width direction in a memory array to generate an empty region formed by a shift-aside region. The width of a conductive interconnection line transmitting a desired signal/voltage is increased in this region. Accordingly, the width of the signal/voltage interconnection line is increased to reduce the resistance without increase in the array occupation area.

Abstract: A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed between the column selection line and a data bus line adjacent to the column selection line. The shielding line electrically shields the data bus line from the column selection line. Therefore, the semiconductor memory device having the high speed data bus can be achieved because the coupling capacitance between the column selection line and the data bus line is reduced.

Abstract: This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit lines in the OPEN state, based on an address signal; a plurality of virtual main grounding lines; and a virtual main grounding line controller for controlling whether to impress a specific voltage on the virtual main grounding lines, impress a grounding voltage on the virtual main grounding lines, or place the virtual main grounding lines in the OPEN state, based on an address signal.

Abstract: An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number≧1 and the second bitline pair comprises n twists 350 and 351, where n is a whole number ≠m. The twists transform coupling noise from adjacent bitline pairs into common mode noise, which results in improved signal margin.

Abstract: Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.

Abstract: First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

Abstract: An object of the invention is to provide a semiconductor memory device suppressing variations in input terminal capacitances of address input terminals and control signal input terminals and enabling a high-speed access. The invention arranges a plurality of terminal capacitance adjusting elements each of which is composed of an ESD element (punch-through element) 6a, 6b or 6c and a terminal capacitance adjusting terminal capacitance element 7a, 7b or 7c through connection changeover aluminum wiring 8a, 8b and 8c in the course of an aluminum wiring 4 from an input terminal to an internal circuit.

Abstract: A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in charge stored on the capacitors. The adverse influences of noise are reduced or eliminated because the noise will generally equally effect both of the complementary capacitors, as well as complementary bit lines connected to the capacitors. Differential sensing of the bit line signals also avoids the influence of noise. A capacitor reference potential conductor distributes substantially equal capacitor reference voltage to each capacitor to allow each capacitor to charge and discharge more uniformly under the influence of noise.

Abstract: An interconnection array is provided including a plurality of line conductors having segments substantially parallel to each other in each of two or more parallel regions such that the composite length of the segments essentially matches said length of the array; the line conductors crossing in one or more crossing regions located between the parallel regions so that no line conductor remains adjacent to the same pair of neighboring line conductors in any of segments of the array; wherein adjacent line conductors in the parallel regions are spaced one pitch from each other and wherein multiple line conductors are offset up or down no more than two pitches in each of the crossing regions.

Abstract: Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.

Abstract: A semiconductor integrated circuit of a low power consumption type has modules (1) to which various supply voltages are provided. In each module (1), cells (3) are grouped into cell rows or cell columns. Only one of a wire (7) of a high supply voltage and a wire (5) of a low supply voltage is formed on each cell row or cell column in the module (1). Various supply voltages are provided into the target cell (3) through the electrical wires (5, 7).

Abstract: Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.

Abstract: A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.

Abstract: A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.

Abstract: Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substantially the same time. The circuitry thus provides for the stress testing of memory cells associated with sense amplifiers connected to only one sub-array within a DRAM or other semiconductor memory. The apparatus also provides an alternative to conventional methods for stress testing memory cells associated with sense amplifiers connected to more than one sub-array within a DRAM or other semiconductor memory.

Abstract: A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.

Abstract: A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks.

Abstract: A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-line pairs to build a folded bit-line structure, a plurality of word lines arranged so as to cross the first bit lines and the second bit lines, and at least one memory cell array in which a plurality of memory cells connected to the first bit lines and the second bit lines are arranged in a matrix, wherein the memory cell array includes a plurality of first areas in which a plurality of memory cells are arranged, and a plurality of second memory areas which are arranged so as to alternate with the first areas and contain no memory cell, and the second memory areas include areas where the first bit lines of the specified number of the bit-line pairs are connected to the second bit lines and the second bit lines are connected to the first bit lines.

Abstract: A multi-bit data storage location 201 is formed at the face of a layer 502 of semiconductor of a first conductivity type. Storage location 201 includes a first transistor 210 having a source/drain region 308 of a second conductivity type formed in layer 502 and a gate 306 disposed insulatively adjacent a first channel area of layer 502 laterally adjacent source/drain region 308. A second transistor 210 is included having a gate 306 disposed insulatively adjacent a second channel area of layer 502. A first capacitor 211 is provided which includes a capacitor conductor 311 disposed insulatively adjacent a first capacitor area 509 of layer 502, first capacitor area 509 being disposed lateral to the first channel area of first transistor 210. A second capacitor 211 is provided which includes a capacitor conductor 211 disposed insulatively adjacent a second capacitor area 509 of layer 502, the second capacitor area 509 disposed lateral to the second channel area of second transistor 210.