Abstract: A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.

Abstract: A memory cell array is divided into a plurality of blocks and sense amplifiers and shift registers are provided for the respective blocks. After a plurality of data sets are read out in the first random access cycle and transferred to each of the shift registers, column switching is made and a plurality of next data sets are read out. Then, the pipeline processing for the data items is effected to serially read out data in the serial access cycle.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: A dual-port, static random access memory (DPSRAM) is configured as a virtual first-in-first-out (FIFO) register under the control of a microprocessor executing a stored program or similar circuit to allow both for conventional random access data buffering between the data source and the data receiver and FIFO-type data buffering in which the data source and data receiver need not generate an address for each data word transferred, but these addresses may be automatically generated in sequence by the buffer using special circuitry.

Abstract: A semiconductor memory device of the present invention comprises, a first memory cell 110, a first data line DLN connected to the first memory cell, a second data line IOT, a first select signal CSL(E) controlling connection/disconnection between the first data line and the second data line, a second memory cell 112, a third data line DTN connected to the second memory cell, a fourth data line IOT, a second select signal CSL (O) controlling connection/disconnection between the third data line and the fourth data line, wherein a timing selecting the first and second memory cells at the writing operation is the same of a timing selecting the first and second memory cells at the reading operation.

Abstract: A synchronous DRAM has cell arrays arranged in a matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks are used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: Described is a programmable logic device with on-chip configuration memory for controlling the state of various programming points. Each programming point includes two or more sequential memory elements, each of which may be programmed to include a data bit associated with a different circuit configuration. The state of an accessed one of the sequential memory elements (i.e., the bit of configuration data currently stored in that memory element) dictates the current FPGA configuration. Alternate configuration bits are stored in the remaining memory elements. The configuration of the FPGA may then be changed by sequentially shifting a data bit from one of the inactive memory cells into the active memory cell. In one embodiment the sequential memory cells are configured in a ring to support alternating between two or more configurations.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Abstract: The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: A buffer memory includes at least one memory including a plurality of memory locations, and at least one write-control circuit. When data is written to one of the plurality of memory locations, the at least one write-control circuit causes at least one bit of validation information to be written to the at least one memory to indicate that the data written to the one of the plurality of memory locations is valid. In response to data being read from the one of the plurality of memory locations, the at least one write-control circuit causes the at least one bit of validation information to be overwritten to indicate that the data stored in the one of the plurality of memory locations is invalid.

Abstract: The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic to eliminate glitches in the inputs to a full/empty flag generator, an almost full/almost empty flag generator or a half-full/half-empty flag generator. The circuit can be extended to generate the logic to eliminate glitches in either direction as the count signals move across a boundary change in a half-full flag generation circuit.

Abstract: A FIFO controller circuit for interfacing data from a device running at one clock speed so that it is compatible with another device or transmission medium running at a different clock speed. A write controller is used to control the writing of data into the FIFO. The write controller is clocked at a first clock speed. A read controller is used to control the reading of data from the FIFO at a second, different clock speed. A counter is incremented when data is written to the FIFO and decremented when data is read from the FIFO. Thereby, the counter represents an amount of memory within the FIFO that is currently available. The decrement signal is generated in the first clock domain and then synchronized to the second clock domain. This provides error-free interfacing, irrespective of any phase differences existing between the two clock signals.

Abstract: In order to shorten the processing time for partially rewrite the data of a SAM array with data of a RAM array without rewriting the content held in the RAM array, and to elevate the integration density, a read transfer gate 11 is added with a mask control function, and there is also added a function of fetching a read mask data SMDr into a serial mask register 13 and of supplying the read mask data SMDr to the read transfer gate 11. The mask data is fetched from an external to the serial mask register 13 through a random data input/output port Prdt, and the control for fetching the mask data is executed on the basis of a serial data latch timing signal SMLT generated in a timing generator 14 on the basis of a row address strobe signal. Thus, the partial data rewriting of the data in the SAM array 8 can be executed in one data transfer cycle.

Abstract: A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

Abstract: A semiconductor memory includes a memory array and an address scrambler. The address scrambler maps sequential input addresses to non-sequential physical addresses for the memory array. In one embodiment, the address scramble includes circuitry that implements a one-to-one function mapping of the logical addresses to physical addresses. Alternatively, the address scrambler includes a pseudo-random series generator that generates a pseudo-random series for the physical addresses. In either case, consecutive memory accesses that would logically correspond to a single row or column are scattered among multiple rows and columns to diminish the length of a gap in a data sequence that would otherwise occur as a result of a defective row or column. For flash memory, the mapping can be restricted so that logical addresses for a sector map to physical address for the same or another sector.

Abstract: An information transfer system for transferring the information recorded on a recording medium includes a first recording medium for recording the information, a second recording medium for recording the information, a transmission unit for transmitting the information recorded on the first recording medium to the second recording medium, and a control unit for causing a writing operation on the second recording medium based upon a control signal for a readout operation from the first recording medium. The information is read out from the first information recording medium as an information transfer origin at the same time as the information is written on the second information recording medium as an information transfer destination. This makes it possible to transfer and duplicate the information at an elevated speed substantially by the readout operation only, so that the information transfer and duplication may be expedited.

Abstract: A circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

Abstract: In a method for testing a counter, the counter is first set at a predetermined initial value. Then, the counter is incremented in response to the clocks. The number of the clocks is counted until a carry is outputted from the counter to provide an actual counted value. The actual counted value is compared to a reference value, which is calculated in advance. And then, the counter is decided whether to be operating normally or not on the basis of the result of the comparison.

Abstract: The configuration of a first-in first-out semiconductor storage device is simplified. A write address generating combinational circuit portion (100A) including no sequential circuits generates write addresses by using read addresses generated by a read counter portion (7).

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: A data buffer includes a number of storing elements, a tree shaped structure of multiplexer elements, a write address generator, and a read address generator. The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal from the clock generator of the receiving clock domain, read addresses for reading out data storing elements in the same order as they were read in.

Abstract: A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer.

Abstract: In a memory device for storing data according to the FIFO principle, an input counter is provided having a value which is modified when data are written into a memory, and having a comparison unit that outputs a status signal concerning presence of data in the memory dependent on a comparison of the counter states. A scanning unit is arranged at the connection between the comparison unit and the input counter. The scanning unit scans the state of the input counter according to a clock signal and outputs the scan result to the comparison unit.

Abstract: In the present invention data from the odd memory cell array is latched to a data-hold circuit at a fast timing, which ignores the delay time of the +1 arithmetic circuit, and outputs that data to the output terminal. Further, when the supplied column address is even, data from the even memory cell array is latched to a data-hold circuit at a fast timing similar to that described above, and when the column address is odd, this data is latched to a data-hold circuit with a delay equivalent to the delay of the +1 arithmetic circuit. In this case, since the output of even output data to an output terminal occurs following the output of odd output data, the overall output operation is not affected comparing to the conventional one. Another aspect of the present invention provides a circuit, which shifts one bit combinations of the second and third bits following the least significant bit in a column address.

Abstract: A semiconductor memory device and method are provided that enhance data output speed of a DRAM or the like by reducing the time difference between the data output operation from a preceding word line and the data output operation from a succeeding word line. The semiconductor memory device includes a memory cell array arranged with multiple memory cells having a corresponding word line and a corresponding bit line, a row decoder for decoding a row address to select and activate a word line of the memory cell array and a sense amplifier for sensing and amplifying the data in a memory cell coupled to the activated word line when the data is applied to the corresponding bit line. The semiconductor further includes first and second latches respectively storing data using the sense amplifier taken from a memory cell coupled to a preceding activated word line and a succeeding activated word line.

Abstract: A high performance, high bandwidth memory bus architecture and module. The module may be a card that includes standard synchronous DRAM (SDRAM) chips and reduces latency and pin count. Four bus pins separate input commands from data and establish parallel system operations. By maintaining "packet" type transactions, independent memory operations can be enhanced from that of normal SDRAM operations. The architecture divides its buses into command and data inputs that are separate from output data.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided.One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.

Abstract: A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer.

Abstract: The function of a line memory can be achieved only with one bit line. As word lines WL.sub.j-1 and WL.sub.j are activated in this order, data has already been read out before new data is written into memory cells MC.sub.j-1,i and MC.sub.j,1. More specifically, a writing process is performed on the same memory cell after a readout process, achieving delay operation as taught in a conventional technique. Further, as both operations of a tristate buffer 11 and a D latch 13 are controlled in accordance with the readout and the writing processes, one bit line serves both as a write bit line and a read bit line.

Abstract: A storage device (SP) which is used for the sequential storage and reading out of a given amount of data. To this end it contains a memory (RAM) which can be read and written into in parallel and a storage control unit (CON) which ensures that storage areas whose data have previously been read out at least once is written into sequentially and successively with a default safety clearance. In a special configuration, an input interface (SPU) and an output interface (PSU) are arranged upstream and downstream, respectively, of the memory (RAM). These interfaces accept and transfer the data serially outwards and in parallel to the memory (RAM), respectively.

Abstract: A dual port memory device and method for outputting serial data at a high speed from a memory array through a data register. The device includes a RAM port and a SAM port. The SAM port receives start column address data from the RAM port during a transfer cycle and the data register is filled with row data from a specified row. During this process, the start column address is latched and incremented, then the incremented address loaded into a serial counter as an initial address to set up a pipeline serial output. After completion of the transfer cycle, the serial counter is controlled by a serial clock and causes column data to be prefetched from the data register and supplied to an output buffer for serial output. Because of the pipeline configuration, data is serially output at a high speed.

Abstract: The invention provides an analog FIFO memory from which a written analog signal can be accurately read by eliminating errors in the analog signal between the write operation and the read operation. Prior to the read operation for reading the analog signal from a memory cell through a memory bus, a reset operation for setting the memory bus at a predetermined potential is conducted so as to remove a charge stored in a parasitic capacitance of the memory bus. The input terminal of a read circuit is set at a predetermined potential, with a write circuit disconnected from the memory bus by using an input circuit and with the read circuit connected with the memory bus by using an output circuit. In this manner, the memory bus is set at the predetermined potential, and the charge stored in the parasitic capacitance is discharged. At this point, a switch in each memory cell is in an off-state, and hence, a charge corresponding to the analog signal can be retained in the memory cell.

Abstract: When stored data of a plurality of memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23, MC30 to MC33) arranged in a matrix are sequentially read out, a reading access control circuit (101) outputs a row address and a column address to a row decoder (102) and a reading bit-line selector (103), respectively, for an access to the memory cells. The reading access control circuit (101) outputs the row address and the column address so that an n-type memory cell may be first selected by the reading bit-line selector (103) after activation of the selected reading word line every time one of the reading word lines (RWL0 to RWL3) is selected by the row decoder (102). With this configuration, data can be sequentially read out at higher speed from a plurality of memory cells arranged in a matrix.

Abstract: There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array including a plurality of memory cells and shift registers and having a plurality of latch circuits connected in series are provided. The shift registers once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits and serially output the held data in the order in which the latch circuits are arranged. The latch circuits sense-amplify the data stored in the memory cells inside the memory cell array.

Abstract: An ATM switch including a multi-port memory is described. The multi-port memory has a dynamic random access memory (DRAM) and input and output serial access memories (SAMs). The multi-port memory includes an array of primary and redundant memory cells. Data transfer buses are described which traverse the array and can be coupled to either the primary or redundant memory cells. Redundant row enable circuitry is described which enables an entire row of redundant memory cells to be substituted for any row of primary memory cells.

Abstract: A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A method and circuit for routing data to registers in an integrated circuit is disclosed. The circuit comprises an I/O port (100) for receiving data and address signals, and a plurality of distributed memory modules (200-900) having registers (210-217). Each memory module is associated with and located adjacent to a circuit functional block. All of the memory modules (200-900) are connected to the I/O port (100) via a single data bus (40).

Abstract: In DRAM, a part of data in a row are rewritten at high speed. The memory device comprises dynamic type cell blocks 11; sense amplifiers 3 for sensing data of the cell blocks 11; latches 2 for storing data; data transfer gates for transferring data between the sense amplifiers 3 and the latches 2; and byte write mask circuit blocks 1 for controlling only the data transfer gates corresponding to only the latches 2 in which data have been written, to transfer data to the sense amplifiers 3. The byte write mask circuit block 1 opens only the transfer gates corresponding to the latches 2 to which data are written and further transfer data from the latches 2 to the sense amplifiers 3. Therefore, when data are required to be written in the cell blocks 11, since only the necessary data are written in the latches 2, it is possible to eliminate wasteful data write to the latches 2, thus enabling a high speed data transfer to the cell blocks 11.

Abstract: A semiconductor memory device is disclosed which can read a plurality of bit units and which can suppress an increase in current consumption and in chip size even if the number of bits serving as a unit of reading is increased. The semiconductor memory device includes a memory cell array having memory cells arranged in a matrix form such that a plurality of columns are divided into a plurality of sections, a plurality of column selection circuits for selecting each of the columns of the memory cell array, a sense amplifier for sense-amplifying data transferred through the data lines, and a column selection control circuit for controlling the plurality of column selection circuits to select one of the plurality of sections of the memory cell array and one of the columns of the sections and to read bit data from the selected column, sequentially.

Abstract: A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.

Abstract: A synchronous DRAM includes a selector which supplies 2 bits of serial data signals from one data input/output terminal to two input/output line pairs as parallel data signals in x8 configuration mode, and supplies 2 bits of parallel data signals from both data input/output terminals directly to two input/output line pairs in x16 configuration mode. Therefore, the synchronous DRAM allows switching of bit configuration, and it takes 2-bits prefetch configuration in x8 configuration mode, and signal pipeline configuration in x16 configuration mode.