Abstract: In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: In a semiconductor memory device in which a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data are used to control operations for reading and writing data, the transmission of write data from FIFO memories to write amplifiers is controlled by the data strobe signal. In addition, switches for connecting write amplifiers with bit lines that are linked to memory cells that correspond to addresses to which write data are to be written are driven without delaying with respect to a timing signal that is synchronized with the system clock. Write data that have been received as burst input are transmitted in parallel from the FIFO memories to the write amplifiers in units of the prefetch number.

Abstract: The present invention involves a synchronous semiconductor memory device having a 4-bit prefetch mode a method of processing a data thereof, comprising first to fourth memory cell arrays each having memory cells, a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data, a data loation control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays, by a sequential method or by an interleaving method, during the write operation, a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays, and location-controlling and outputting them in response the first to fourth decoding signals, by a sequential method or by an interleaving method, during a read

Abstract: A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

Abstract: Testing an integrated circuit IC (2) with an embedded or integrated non-volatile memory (3), in particular an embedded memory, an EPROM or EEPROM, is particularly difficult because mass production and low prices and minimal profit margins require that the testing, which usually requires expensive and large equipment, can be done in a minimum of time. Usually, the testing of an embedded memory (3) is a kind of bottleneck during manufacturing. The present invention describes a test structure and design and an associated test method which minimize this test time for an embedded memory.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: Integrated circuit memory devices include a word line driver circuit electrically coupled to a plurality of rows of normal memory cells and at least one row of spare memory cells that can be used to replace normal rows having defective cells therein. The word line driver circuit includes a spare word line driver that is electrically coupled to the at least one row of spare memory cells. The spare word line driver includes a programmable address decoder, which generates a spare word line driver enable signal and is responsive to a plurality of row addresses, and a selector switch that is responsive to the spare word line driver enable signal. To assist in performing a multi-row address test, a spare word line driver enable signal precharger is provided that resets the spare word line driver enable signal to a logic level that turns on the selector switch when the memory device is undergoing a multi row address test.

Abstract: Disclosed is a data output driver which improves the timing margin of a memory operation by reducing skew related to data output in a semiconductor memory device. A register receives and stores a plurality of first parallel data in synchronization with clock signal and outputs a plurality of second parallel data. A controller compares a plurality of parallel data currently inputted to register with a plurality of parallel data previously inputted to register in response to delayed clock signal, and calculates the number of data transitions based on the comparison result, and generates a control signal according to calculated number of data transitions. A clock signal delay part delays clock signal according to a logic level of control signal in order to generate a pair of corrected clock signals. A data selecting part selectively outputs odd or even numbered data among the plurality of second parallel data. An output driving part buffers and outputs output data of the data selecting part.

Abstract: An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD, /WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).

Abstract: A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n×n (e.g., four) memory cells alternatively selected according to a combination of n (e.g., two) pairs of positive and negative phase signals and provided to output the positive and negative phase signals according to the data stored in the selected memory cell, variable wiring unit provided with signal lines for inter-connecting the variable logical circuits and switching elements for connecting/disconnecting signal lines inter-secting to each other, a wiring connection state storage memory circuit where the states of the switching elements are stored.

Abstract: There is provided a display driver incorporating a RAM in which a plurality of memory cells having a three-port configuration can be provided within an interval of output electrodes thereof, and a display unit and an electronic apparatus utilizing the same. The memory cells include a flip-flop comprised of first and second inverters. A first node of the flip-flop is connected to a CPU bit line and an RGB bit line through an N-type MOS transistor. A P-type MOS transistor and an N-type MOS transistor are connected to a second node of the flip-flop. The N-type MOS transistor is connected to a ground potential level at the source terminal thereof. A set signal for each pixel is supplied to the gate terminal of only the flip-flop associated with the pixel to be written, and the set signal sets the second node at the ground potential level.

Abstract: A content addressable memory (CAM) device providing higher integration density, high operation speed and low power consumption. The CAM device comprises a memory cell connected between first and second nodes, first and second data lines for transmitting first and second data signals to the first and second nodes, respectively, and first and second switching devices serially connected between a match line and a reference voltage, wherein the first switching device is controlled by the first data signal and a voltage of the first node and the second switching device is controlled by the second data signal and a voltage of the second node.

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.

Abstract: A novel FIFO data structure in the form of a multi-dimensional FIFO. For a rectangular multi-dimensional FIFO, data items are received at an input of an N-row-by-M-column FIFO array of cells and transferred to an output, via a predetermined protocol of cell transfers, in the same order as received. Transfer rules or protocol are controlled by a control circuit implemented using asynchronous pipeline modules or a control circuit relying upon transition signaling.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: The circuit configuration for storage management and for the execution of user programs in small control units using a microcontroller (2). A microcontroller (2) has a central processing unit, a volatile memory, a non-volatile memory and an interface. An additional non-volatile readable and writeable memory unit is configured as a serial memory unit and is,connected to the microcontroller as a separate unit via the interface. Different methods are described, for executing user programs using the circuit configuration. In a first method, the entire user program is read out from the separate memory and is serially interpreted by the microcontroller. In a second method, the entire user program is copied into and afterward directly interpreted by an internal memory of the microcontroller during the runup phase of the flow of control.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A semiconductor memory device is comprised of a plurality of sense amplifiers. The sense amplifiers are arranged in two amplifier columns. The two amplifier columns are disposed between two cell columns of cell plates. An address circuitry, an ATD circuitry, and a delay circuitry are disposed between an input pin row and the two cell columns. An ATD pulse synthesizer Is disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.

Abstract: A programmable non-volatile data storage calibration circuit stores a calibration code for a temperature sensor circuit of an IC, comprising a programmable array of addressable bi-state, bi-stable first circuit elements each comprising a fusible resistor. A power supply controlled by a data input signal addresses the first circuit elements to be switched from a first to a second state in the fusible resistor state, the supply, and a clock signal applied to an I/O terminal clocks the data input signal to the interpreter circuit. The interpreter circuit sequentially selects and addresses the first circuit elements and enables switching of the first circuit elements when the supply voltage is at its maximum, blowing a selected fusible resistor. A second, similar circuit element is switched to its second state after programming the calibration circuit to prevent its further programming.

Abstract: A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different areas on a chip so that the circuit layout is not optimized. The disclosed cell combines them in the same area, saving more than 20% of the area.

Abstract: An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.

Abstract: A method and apparatus for storing and retrieving data in a second, or higher, order prefetch architecture memory integrated circuit. The method includes storing multiple bits of data in memory cells at various electrical distances from an output buffer and retrieving those memory bits concurrently for output. By outputting the bits in a fixed burst order, according to which a bit from a memory cell closer to the output buffer is output before a bit from a memory cell farther from the output buffer, the output time of the data bit from the closer memory cell can be used to mask a portion of the transit time of the bit from the farther memory cell. The apparatus includes memory cells at various locations for storing data bits, an address decoder adapted to store and retrieve multiple bits in a fixed burst order, and a multiplexer.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: Space, power and performance are improved by a memory device having multiple modes of operation for elastic data transfer. The memory device is comprised of first and second elastic store memory blocks, each containing 16 (18 bit) memory locations, and a write/read decoder. The first memory block receives write data from a first (18 bit) input data bus, and outputs two memory locations (36 bits) of read data onto a four memory location (72 bit) output data bus. The second memory block receives write data from multiplexed first and second (18 bit) input data buses and outputs two memory locations of read data onto the four memory location (72 bit) output data bus. The write address decoder receives a 5 bit write address, wherein the write address decoder will, as a function of a mode signal for effectively changing the address space for writing data, direct write data received at the data inputs of the first and second elastic store blocks to the correct memory locations.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible ×4N, ×2N and ×N bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory component having a memory core for storing data therein. The memory component comprises a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory component also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

Abstract: A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.

Abstract: The present invention creates a memory chip, a memory component and a corresponding memory module. The memory chip is equipped with a multiplicity of memory cells and has an an [sic] array (20) of fuses and anti-fuses respectively, which can be written to and read individually in order to store specification information.

Abstract: An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.

Abstract: A dual FIFO architecture is described which allows internal read and write operations in a DRAM memory device to be decoupled from the read and write operations associated with the processor-memory bus. The application of separate read and write FIFO buffers interfaced with a plurality of memory banks on a DRAM memory device thus compensates for mismatches in communications speed that may exist between the rate at which data is provided to the memory banks from the processor-memory bus and likewise, the rate at which the memory banks can provide data to the processor-memory bus. Furthermore, the decoupling of internal memory operations with external reads and writes permits prioritization of read and write commands. Since the FIFOs serve directly as a data buffer to the memory banks, high speed computer operations is permitted because the microprocessor and the memory bus may operate at their own natural frequency without being restricted by the speed of the DRAM memory device.

Abstract: A data synchronizer (210) transfers data from a data sending circuit (120) to a data receiving circuit (130). The data sending circuit is synchronous with a first clock (SCLK), and a data receiving circuit is synchronous with a second clock (RCLK). The two clocks have equal frequencies but may be out of phase. The synchronizer includes a circular FIFO. The FIFO entries (FF0-FF3) are written synchronously with the first clock (SCLK). The entries' outputs are connected to a multiplexer (230) whose select signals (RSEL0-RSEL3) are generated synchronously with the second clock (RCLK). Multiple entries make their data items available to the multiplexer at the same time. The sender (120) writes a data item and a data valid flag to the FIFO in each cycle of the first clock. The receiver (130) reads the FIFO in each cycle of the second clock.

Abstract: A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method comprising: storing a plurality of configuration data in the non-volatile memory and, providing power to the volatile memory. After providing power to the volatile memory, serially loading the configuration data into the registers of the volatile memory to configure the semiconductor device.