Abstract: A cache DRAM includes a main memory, a main cache memory for storing data which is accessed at a high frequency out of data stored in the main memory, a main tag memory for storing an address in the main memory of the data stored in the main cache memory, a subcache memory for always receiving data withdrawn from the main cache memory for storage and supplying the stored data to the main memory when the main memory is in a ready state, and a subtag memory for storing an address in the main memory of the data stored in the subcache memory. Since the subcache memory serves as a buffer for data to be transferred from the main cache memory to the main memory, the main cache memory withdraws data to the subcache memory even if the main memory is in a busy state.

Abstract: A memory device, comprising: an interface block for transferring a packet data of selected bits through every data pads at a negative edge and a positive edge of clock signals; a data shift block, in accordance with a load signal from the interface block, for converting the packet data in serial transferred through the interface block and writing the converted data into the core block or converting packet data read from the core block into the serial data and transferring the converted data with a packet type through data pads at a negative edge and a positive edge; and a load signal control means for controlling the load signal to be provided into from the interface block to the data shift block in data read in accordance with a confirming signal for indicating whether the data from the core block is ready to read, or not.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: A test circuit for functionally testing memory devices. The test circuit loads a plurality of data bits into the memory device under test. The test circuit subsequently reads the data bits stored in the memory cells, and detects if the logic level of the data bits read is the complement of the logic level written: The logic level is detected over a duration during which at least two data bits are read.

Abstract: A FIFO circuit with a reduced number of buffers connected to output ports and thereby lowering parasitic capacitance. The FIFO circuit includes an input register for storing data therein supplied from a plurality of input ports. A shifter rearranges the data supplied from the input register and a shift register stores therein and shifts the data supplied from the shifter. A selector circuit selects either the data from the input register or the data from the shift register such that valid data fill places from a least significant side of the output ports. A control circuit controls the input register, the shift register, the shifter, and the selector circuit.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.

Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Abstract: A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device.

Abstract: Embodiments of the present invention may provide methods of controlling a memory device and memory devices including a memory array having an internal address input which specifies a location in the memory array accessed during read operations and write operations. An external address input receives an address value from a device external to the memory device. The received address value may be utilized to randomly access the memory array. An address register/restart address counter is operatively associated with the memory array and the external address input and configured to store a start address for at least a write operation to the memory array, to selectively generate a series of internal addresses to access the memory array based on the stored start address and to selectively return to the stored start address as a start address of a subsequent operation to access the memory array.

Abstract: The synchronous semiconductor memory device related to the present invention is a synchronous semiconductor memory device in which for one data read signal, the respective data corresponding to a plurality of addresses are sequentially read out from a memory cell in synchronism with an external clock signal, and which comprises a control circuit which executes control according to an externally inputted control signal so as to output only the data corresponding to one address from the memory cell for one data read signal.

Abstract: A first data store circuit is coupled to first and second voltage nodes of first and second voltage levels, respectively, and a control circuit outputs a transfer signal and a switching signal. A data transfer circuit is coupled between the first data store circuit and a second data store circuit and selectively transfers the data in the first data store circuit to the second data store circuit in response to the transfer signal. A first conductive line supplies the first voltage level to the second data store circuit and a second conductive line supplies the second voltage level to the second data store circuit. A first switch circuit is coupled between the second voltage node and the second conductive line and selectively connects the second voltage node to the second conductive line in response to the switching signal. Also a resistive element is coupled between the second conductive line and the first voltage node.

Abstract: The first-in first-out storage device has a write counter for counting as a write address the number of data write operations of a write side circuit, a read counter for counting as a read address a number of data read operations of a read side circuit, a RAM which stores data input from the write side circuit into a storage region that corresponds to the write address when the write side circuit has performed the write operation and outputs the data stored in the storage region that corresponds to the read address to the read side circuit when the read side circuit has performed the read operation, a full-state detection unit which detects whether the write operation of the write side circuit needs to be restricted or not based on the write address and read address, a flip-flop which outputs a detection result obtained by the full-state detection unit to the write side circuit in synchronization with a write clock signal based on which the write side circuit operates, an empty-state detection unit which dete

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: A queue includes a data multiplexer having an output and at least two inputs and a plurality of data latches. The data latches include at least a first data latch and a second data latch, which each have a data input and a data output. The data output of the first data latch is coupled to a first input of the data multiplexer, and the output of the data multiplexer is coupled to the data input of the second data latch. A data value to be stored in the queue is received at a second input to the data multiplexer. In response to one or more control signals, the data value is latched into at least one of the first and second data latches, thereby storing the data value in the queue. Depending upon the design of the control logic, the queue can implement either first in, first out (FIFO) or last in, first out (LIFO) behavior.

Abstract: Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. In one embodiment, a hierarchical one of the plural primary nodes includes plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line. In another embodiment, a hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line.

Abstract: An integrated circuit first-in, first-out (“FIFO”) memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory (“DRAM”) array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory (“SRAM”) row, or register, interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: Integrated circuit memory devices include first and second spaced-apart memory banks in an integrated circuit substrate. A pad block in the integrated circuit substrate is located between the first and second spaced-apart memory banks. An input/output block in the integrated circuit substrate is connected to the pad block to receive input data from external of the integrated circuit memory device via the pad block and to transmit output data to external of the integrated circuit memory device via the pad block. A delay locked loop in the integrated circuit substrate is responsive to an external clock signal to generate an internal clock signal. An interface logic block in the integrated circuit substrate is responsive to the internal clock signal to control the first and second memory banks and the input/output block in response to the internal clock signal. A single data shift block in the integrated circuit substrate is located between the pad block and one of the first and second spaced-apart memory banks.

Abstract: Semiconductor memory device which can support a DDR SDRAM latency mode like 2.

Abstract: A synchronous memory comprises a memory cell array having a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals.

Abstract: A dual-port memory includes a dummy memory cell associated with a dummy output line and with a precharge transistor, the output of the dummy cell being at "0". A dummy read transistor is turned on by the active state of the read selection signal and connects the output of the dummy cell to the dummy output line. Circuitry is provided for turning on the output transistors of the memory when the state of the dummy output line reaches a predetermined switching threshold of an inverter.

Abstract: A read/write electronic memory bank 10, including a plurality of memory units 22-28 and 12-18 which receive a common clock signal having a repetitive clock cycle and have a common input port 20, 21 and a common output port 30, 31. The units function such that in each clock cycle an input word is written to the memory bank 10 from the input port 20, 21 and an output word is read from the memory bank 10 to the output port 30, 31. Each memory unit 22-28 and 12-18 includes a single-port random-access memory (RAM) device 22-28 and a first-in first-out (FIFO) buffer 12-18, such that when the output word is to be read from the same memory unit 22-28 and 12-18 to which the input word is to be written in a given clock cycle, one of the input and output words is passed between the respective port 20, 21, 30, 31 of the memory bank 10 and the FIFO buffer 12-18, instead of between the respective port 20, 21, 30, 31 of the memory bank 10 and the RAM device 22-28.

Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.

Abstract: Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than or equal to the write address. When the write address for the FIFO queue is less than the read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than the write address plus a maximum depth of the FIFO queue. A first read transaction of the first transaction size from the FIFO queue is performed only when the first condition flag is true.

Abstract: An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

Abstract: According to the current invention, there is provided a system for transferring data into and out of a first-in, first-out (FIFO) data buffer. The buffer has a read pointer and a write pointer. The system comprises a comparator circuit, multiple counter blocks, and multiple flag registers. The counter blocks and flag registers are connected to a system clock to provide timing information and capacity indications to the comparator. The comparator circuit continuously monitors the multiple counter blocks, thereby tracking buffer pointer positions. The flag registers indicate relative buffer capacity and provide early indication to the system that the buffer is almost full or almost empty in appropriate conditions. The comparator circuit continuously evaluates the read and write counter blocks and the flag registers to determine the ability of the buffer to accept or transmit data.

Abstract: The present invention relates to a high speed empty flag generator and a method of generating a high speed empty flag which are achieved by generating a pre-empty flag in a clock ahead of a read address which is identical to a write address and by generating an empty flag as soon as a read address identical to the write address is generated after an elapse of one clock. The present invention includes a subtracter generating upper N-1 bits of a value resulted from subtracting 1 from a write address of N bits, a pre-empty flag generator generating an pre-empty flag when an output of upper N-1 bits of a rear address of N bits and an output of N-1 bits of the subtracter coincide by comparison, and a main empty flag receiving said pre-empty flag wherein the main empty flag generator generating an empty flag at a generating point of a first read signal after the pre-empty flag.

Abstract: A pull through FIFO memory structure consisting solely of latches and logic circuits wherein the FIFO structure includes an empty/full bit for determining whether each cell in the FIFO structure includes FIFO data. If a cell is identified as not containing FIFO data, then each previous cell's FIFO data will be advanced during a clock signal.

Abstract: A serial memory device includes a Y decoder and sensing circuitry which provide a predictive mode of operation, wherein data sensing of a target memory location begins before its address is fully known by sensing the data lines of a number of possible memory locations including the target location. The method and apparatus includes sensing first data bits of possible memory locations when some but not all of the address bits are clocked in. As additional address bits are clocked in, additional data bits are sensed. By the time the target address has been fully received, sensing of its first data bits will have completed so that serial outputting of the target memory can begin on the next clock. This sense-ahead feature permits an increase in the internal clock frequency without affecting external timing constraints imposed by the various serial memory device interfaces.

Abstract: A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.

Abstract: A buffer comprising a plurality of storage elements, a write pointer configured to indicate a particular storage element to write data received from an input data stream and a plurality of read pointers, each configured to indicate a particular data location to read data from to generate a number of output data streams. The input data stream and the output data streams may be part of a data communications device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array. In an alternative embodiment, the FIFO memory device includes a "Retransmit" feature which allows data to be read from the device multiple times as well as the Read Pointer to be selectively placed under user control.

Abstract: A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillation frequency of the FIFO control ring may be increased to accommodate higher-speed chips, while maintaining synchronization of clock pulses at each stage of the FIFO control ring.

Abstract: A FIFO memory apparatus of the present invention includes an array of registers including a plurality of stacked subarrays. A first plurality of multiplexers is provided including one multiplexer for receiving data from each one of the subarrays. A second plurality of multiplexers is also provided each for receiving data from two other multiplexers. One of the second plurality of multiplexers supplies an output for the FIFO memory apparatus, while each of the others, in pairs, supply other multiplexers of the apparatus. The invention uses a four-way interleaved memory architecture for pre-decoding the FIFO read pointer and driving out data from one of the sixteen deep 32-bit wide registers, in advance. In this way, the final stage of the timing critical path is from the Q output of a toggle flip-flop to a two-to-one multiplexer and output buffer.

Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A integrated circuit (100) includes a plurality of cores (110, 120). With each core (110, 120) is associated a TCB (112, 122) for controlling the core in a test mode thereof. Each TCB has a shift register (220) for holding test control data. The TCBs (112, 122) are serially linked in a chain (140) so that, the test control data can be serially shifted in. A system TCB (130) is provided in the chain (140) comprising a further shift register (220). The system TCB (130) is connected to each TCB (112, 122) for, after receiving a particular set of test control data in its shift register (220), providing the TCBs (112, 122) with a system test hold signal for switching between a shift mode and an application mode of the TCBs (112, 122).

Abstract: The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer.

Abstract: It is an object of the invention to provide a semiconductor memory capable of masking arbitrary number of data of a plurality of input-output data. To achieve this object, the semiconductor memory comprises a memory part for storing therein a plurality of data, a data control circuit to which input data mask control signals and an output data mask control signal are inputted for masking arbitrary data of a plurality of consecutive data which are written on the memory part in response to the input data mask control signals, and for masking arbitrary data of a plurality of consecutive data which are read from the memory part in response to the output data mask control signal, and a data mask control circuit for generating the input data mask control signals, and the output data mask control signal in response to the input-output data mask control signals.

Abstract: A system and method for storing data in a linked list memory architecture maintains several key list parameters. When data to be stored is received, a memory manager determines the list in which the data belongs and retrieves several of the parameters. The parameters retrieved indicate the address of the current location at which the received data is to be stored and the address of the next location that is to be linked to the current list. The memory manager writes the data to the current location pointed to by the first address and writes the second address into a pointer field in that current location. Because the address of the next location in the list is determined before data is written to the current location, this next address can be written in the same cycle in which the data is written.

Abstract: A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.

Abstract: A FIFO unit for buffering serial communications includes a register and a unit for maintaining a single pointer. The single pointer functions as an IN pointer during writes and an OUT pointer during reads. The same circuitry maintains the pointer for both reads and writes to the FIFO. This circuitry preferably includes a single counter. If an error occurs during reading, the single pointer can be reinitialized and reading restarted, without loss of data. The register is not erased until reading is complete.

Abstract: Data buffering apparatus comprises a data memory in which input data are written to the memory in contiguous groups at memory addresses defined by a write pointer and data are read from the memory at a memory address defined by a read pointer; and means for writing a dummy group of data at the end of at least some of the input data groups, the dummy groups of data being read from the memory and discarded before a subsequently written input data group is read.

Abstract: A semiconductor dynamic random access memory device serially reads out data bits from and serially writes data bits into memory cells through a long burst cycle, and the data bits are transferred between a read/write data bus to data latch circuits, between the data latch circuits and the main/sub sense amplifiers and the main/sub sense amplifiers and the sub-bit line pairs; while the data bits are being stepwise transferred between the memory cells and the read/write data bus, an internal timing controller not only provides activation timings and deactivation timings to the main-sub sense amplifiers and transfer gate arrays but also the starting point and the end point of the long burst cycle so that the semiconductor dynamic random access memory device is fabricated on a relatively small semiconductor chip.

Abstract: A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.