Including Magnetic Element Patents (Class 365/225.5)
  • Patent number: 8102703
    Abstract: A magnetic tunnel junction, including a reference layer having a fixed magnetization direction, a first storage layer having a magnetization direction that is adjustable relative to the magnetization direction of the reference layer by passing a write current through said magnetic tunnel junction, and an insulating layer disposed between said reference layer and first storage layer; characterized in that the magnetic tunnel junction further comprises a polarizing device to polarize the spins of the write current oriented perpendicular with the magnetization direction of the reference layer; and wherein said first storage layer has a damping constant above 0.02. A magnetic memory device formed by assembling an array of the magnetic tunnel junction can be fabricated resulting in lower power consumption.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: January 24, 2012
    Assignee: Crocus Technology
    Inventors: Jean-Pierre Nozières, Bernard Dieny
  • Patent number: 8098538
    Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Daniel Seymour Reed, Yong Lu, Song S. Xue, Dimitar V. Dimitrov, Paul E. Anderson
  • Patent number: 8093668
    Abstract: A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda
  • Patent number: 8077502
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 13, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 8077503
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 13, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 8054706
    Abstract: A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Phillip Mark Goldman, Muralikrishnan Balakrishnan
  • Patent number: 8045366
    Abstract: Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Haiwen Xi, Kaizhong Gao, Olle Heinonen, Wenzhong Zhu
  • Patent number: 8004881
    Abstract: In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 23, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Shiqun Gu, Xia Li, Seung H. Kang
  • Patent number: 7995383
    Abstract: A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Xiaochun Zhu
  • Patent number: 7995378
    Abstract: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Cheng Zhong, Dongkyu Park, Mohamed H. Abu-Rahma
  • Publication number: 20110149670
    Abstract: Provided are a spin valve device including graphene, a method of manufacturing the spin valve device, and a magnetic device including the spin valve device. The spin valve device may include at least one of a graphene sheet or a hexagonal boron nitride (h-BN) sheet between a lower magnetic layer and an upper magnetic layer. The graphene sheet may have a single layer structure or a multilayer structure. The spin valve device may further include a spacer between the lower magnetic layer and the graphene sheet. The spin valve device may further include a spacer between the graphene sheet and the upper magnetic layer.
    Type: Application
    Filed: August 24, 2010
    Publication date: June 23, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Sun-ae Seo, Yun-sung Woo, Hyun-jong Chung
  • Patent number: 7957181
    Abstract: This magnetic memory with a thermally-assisted write, every storage cell of which consists of at least one magnetic tunnel junction, said tunnel junction comprising at least: one magnetic reference layer, the magnetization of which is always oriented in the same direction at the time of the read of the storage cell; one so-called “free” magnetic storage layer, the magnetization direction of which is variable; one insulating layer sandwiched between the reference layer and the storage layer. The magnetization direction of the reference layer is polarized in a direction that is substantially always the same at the time of a read due to magnetostatic interaction with another fixed-magnetization layer called the “polarizing layer”.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 7, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Nozieres, Ricardo Sousa, Bernard Dieny, Olivier Redon, Ioan Lucian Prejbeanu
  • Patent number: 7952906
    Abstract: An information storage device includes a writing magnetic layer including a magnetic domain wall. An information storing magnetic layer is connected to the writing magnetic layer, and includes at least one magnetic domain wall. The information storage device also includes a reader for reading data recorded in the information storing magnetic layer. The connection layer includes a first portion with a first width adjacent to the writing magnetic layer and a second portion with a second width adjacent to the at least one information storing magnetic layer. The first width is less than the second width.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chee-kheng Lim
  • Patent number: 7952918
    Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-yeong Cho, Yun-seung Shin
  • Patent number: 7940592
    Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 10, 2011
    Assignee: Seagate Technology LLC
    Inventors: Daniel Seymour Reed, Yon Lu, Song S. Xue, Dimitar V. Dimitrov, Paul E. Anderson
  • Patent number: 7936627
    Abstract: A magnetoresistance effect element according to the present invention comprises a magnetization free layer 1 and a magnetization fixed layer 3 connected to the magnetization free layer 1 through a nonmagnetic layer 2. The magnetization free layer 1 includes a magnetization switching region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization switching region 13 having reversible magnetization overlaps with the magnetization fixed layer 3. The first magnetization fixed region 11 having first fixed magnetization is connected to one end 13a of the magnetization switching region 13. The second magnetization fixed region 12 having second fixed magnetization is connected to the other end 13b of the magnetization switching region 13. The first magnetization fixed region 11 and the magnetization switching region 13 form a three-way intersection, and the second magnetization fixed region 12 and the magnetization switching region 13 form another three-way intersection.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 3, 2011
    Assignee: NEC Corporation
    Inventor: Shunsuke Fukami
  • Patent number: 7936595
    Abstract: Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic multilayer film. The cross section of the metal core is a corresponding circular or oval. A MRAM is made of the closed magnetic multilayer film with or without a metal core. The close-shaped magnetic multilayer film is formed by micro process method. The close-shaped magnetic multilayer film can be used broadly in a great variety of device that uses a magnetic multilayer film as the core, such as MRAM, magnetic bead in computer, magnetic sensitive sensor, magnetic logic device and spin transistor.
    Type: Grant
    Filed: December 31, 2006
    Date of Patent: May 3, 2011
    Assignee: Institute of Physics, Chinese Academy of Sciences
    Inventors: Xiufeng Han, Ming Ma, Qihang Qin, Hongxiang Wei, Lixian Jiang, Yunan Han
  • Patent number: 7936597
    Abstract: The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Thomas W. Clinton, Michael A. Seigler, Mark W. Convington, Werner Scholz
  • Patent number: 7933146
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 26, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 7929370
    Abstract: We describe the structure and method of formation of a STT MTJ or GMR MRAM cell element that utilizes transfer of spin torque as a mechanism for changing the magnetization direction of a free layer. The critical current is reduced by constructing the free layer as a lamination comprising two ferromagnetic layers sandwiching a coupling valve layer. When the Curie temperature of the coupling valve layer is above the temperature of the cell, the two ferromagnetic layers are exchange coupled in parallel directions of their magnetization. When the coupling valve layer is above its Curie temperature, it no longer exchange couples the layers and they are magnetostatically coupled. In the exchange coupled configuration, the free layer serves to store data and the cell can be read. In its magnetostatically coupled configuration, the cell can be more easily written upon because one of the layers can assist the spin torque transfer by its magnetostatic coupling.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 19, 2011
    Assignee: MagIC Technologies, Inc.
    Inventor: Tai Min
  • Patent number: 7920416
    Abstract: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Daniel C. Worledge
  • Publication number: 20110063899
    Abstract: In order to obtain a memory cell of size 4 F2 to realize cross-point type memory, a magnetic memory element is used having a spin valve structure including a free layer 5, nonmagnetic layer 4, and layer 3. The layer or the free layer includes an N-type ferrimagnetic material, and the magnetic compensation point of the N-type ferrimagnetic material is lower than the temperature reached by the layer when a certain write pulse is applied to control the combination of magnetizations of the free layer and layer, and higher than the temperature reached by the layer when another write pulse is applied. These write pulses can have the same polarity.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 17, 2011
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD
    Inventor: Yasushi Ogimoto
  • Patent number: 7898849
    Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology, LLC
    Inventors: Thomas William Clinton, Werner Scholz
  • Patent number: 7869264
    Abstract: An information storage device includes a record head and a data recording medium. The record head includes a magnetic substance having magnetic domain walls and records data in the data recording medium. In a method of operating the information storage device, a first high frequency current or a high frequency magnetic field is supplied to the magnetic substance while magnetic domain walls of the magnetic substance are moved.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoo-san Lee, Chee-kheng Lim, Hoon-sang Oh
  • Patent number: 7869265
    Abstract: A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: January 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuui Shimizu, Tatsuya Kishi
  • Patent number: 7859881
    Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Katsuyuki Fujita, Yuui Shimizu
  • Patent number: 7859896
    Abstract: A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Kurotsuchi, Norikatsu Takaura, Yoshihisa Fujisaki
  • Patent number: 7855911
    Abstract: Spin torque magnetic logic devices that function as memory devices and that can be reconfigured or reprogrammed as desired. In some embodiments, the logic device is a single magnetic element, having a pinned layer, a free layer, and a barrier layer therebetween, or in other embodiments, the logic device has two magnetic elements in series. Two input currents can be applied through the element to configure or program the element. In use, logic input data, such as current, is passed through the programmed element, defining the resistance across the element and the resulting logic output. The magnetic logic device can be used for an all-function-in-one magnetic chip.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: December 21, 2010
    Assignee: Seagate Technology LLC
    Inventors: Xiaohua Lou, Dimitar V. Dimitrov, Song S. Xue
  • Patent number: 7791929
    Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-yeong Cho, Yun-seung Shin
  • Patent number: 7787289
    Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: August 31, 2010
    Assignee: Magsil Corporation
    Inventors: Krishnakumar Mani, Jannier Maximo Roiz Wilson, Anil Gupta, Kimihiro Satoh
  • Patent number: 7782663
    Abstract: A data storage device includes a magnetic layer having a plurality of magnetic domains, a write head provided at an end portion of the magnetic layer, a read head to read data written to the magnetic layer, and a current controller connected to the write head and the read head. A method of operating the data storage device includes reading data of an end portion of the magnetic layer using a read head provided at the end portion of the magnetic layer in which a write head is provided at the other end portion thereof, moving a magnetic domain wall of the magnetic layer by a distance corresponding to the length of one magnetic domain toward the end portion, and writing the read data to the other end portion of the magnetic layer using the write head and a current controller provided between the write head and the read head.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-su Kim
  • Patent number: 7764539
    Abstract: A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When RMTJ1>RMTJ2, the bit cell has a “0” state, and when RMTJ1<RMTJ2, the bit cell has a “1” state.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: July 27, 2010
    Assignee: MagIC Technologies, Inc.
    Inventors: Yimin Guo, Jeff Chien
  • Publication number: 20100182837
    Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Yang Li, Hongyue Liu, Song S. Xue
  • Patent number: 7760535
    Abstract: A method and structure for depinning a domain wall that is in spatial confinement by a pinning potential to within a local region of a magnetic device. At least one current pulse applied to the domain has a pulse length sufficiently close to a precession period of the domain wall motion and the current pulses are separated by a pulse interval sufficiently close to the precession period such that: the at least one current pulse causes a depinning of the domain wall such that the domain wall escapes the spatial confinement; and each current pulse has an amplitude less than the minimum amplitude of a direct current that would cause the depinning if the direct current were applied to the domain wall instead of the at least one current pulse. The pulse length and pulse interval may be in a range of 25% to 75% of the precession period.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stuart Parkin, Luc Thomas
  • Patent number: 7760538
    Abstract: A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: July 20, 2010
    Assignee: Xilinx, Inc.
    Inventor: Sunhom Paak
  • Patent number: 7755930
    Abstract: Provided are a semiconductor memory device and a magneto-logic circuit which change the direction of a magnetically induced current according to a logical combination of logic states of a plurality of input values. The semiconductor memory device comprises a current driving circuit, a magnetic induction layer, and a resistance-variable element. The current driving circuit receives a plurality of input values and changes the direction of a magnetically induced current according to a logical combination of logic states of the input values. The magnetic induction layer induces magnetism having a direction varying according to the direction of the magnetically induced current. The resistance-variable element has a resistance varying according to the direction of the magnetism induced by the magnetic induction layer.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee-won Kim, Young-jin Cho, Hyung-soon Shin, Sung-hoon Choa, Seung-jun Lee, In-jun Hwang
  • Patent number: 7755932
    Abstract: An object of the present invention corrects fluctuation of a writing current between cells in a magnetic random access memory using spin torque magnetization reversal. The present invention includes a magneto-resistive effect element that is disposed between a bit line and a word line, a first variable resistance element that is connected to one end of the bit line, a second variable resistance element that is connected to the other end of the bit line, a first voltage applying unit that applies voltage to the first variable resistance element, and a second voltage applying unit that applies voltage to the second variable resistance element, when a writing operation is performed, an offset magnetic field is applied to a free layer of the magneto-resistive effect element by flowing a variable current between the first voltage applying unit and the second voltage applying unit based on a predetermined resistance value.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 13, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kenchi Ito, Jun Hayakawa, Katsuya Miura
  • Patent number: 7751235
    Abstract: A semiconductor memory device includes first to fourth resistance change elements sequentially arranged apart from each other in a first direction, a first electrode which connects one terminals of the first and second resistance change elements, a second electrode which connects one terminals of the third and fourth resistance change elements, a bit line which connects the other terminals of the second and third resistance change elements, first to fourth word lines respectively paired with the first to fourth resistance change elements, arranged apart from the first and second electrodes, and running in a second direction, a first current source which supplies a first electric current to a chain structure, when writing data in a selected element, and a second current source which supplies a second electric current to a selected word line which corresponds to the selected element, when writing the data in the selected element.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao
  • Patent number: 7728384
    Abstract: A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers positioned adjacent to the opposite sidewalls of the contact define the size of the single crystal self-aligned diode. A first and second metal silicide lines are positioned adjacent to the first and second spacers, respectively. The single crystal self-aligned diode, defined in a silicon substrate, includes a bottom implant (BI) region and a contact implant (CI) region. The CI region is surrounded by the BI region except for a side of the CI region that aligns the surface of the silicon substrate. A fabrication method, a read method, two programming methods for the MRAM cell are also disclosed.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 1, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Chiahua Ho, Yenhao Shih, Hsiang-Lan Lung
  • Patent number: 7710770
    Abstract: A serial magnetic mass storage device and associated data storage method of the kind in which data is encoded in single magnetic domains in nanowires. In the invention, the nanowires are provided with a large number of notches along their length to form domain wall pinning sites. Moreover, the notches are addressed in groups (A, B, C) by heating electrodes. By alternately heating the notches hosting head-to-head and tail-to-tail domain walls in synchrony with alignment and anti-alignment of an operating field (H) along the nanowire the magnetic domains are moved along the nanowire by alternate movement of the head-to-head and tail-to-tail domain walls in caterpillar or worm-like motion in which the domains are incrementally lengthened and shortened by one inter-notch distance as they move along the nanowires under the joint coordinated action of the heating and alternating operating field.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: May 4, 2010
    Assignee: Ingenia Holdings UK Limited
    Inventors: Russell Paul Cowburn, Dorothee Petit, Dan Read, Oleg Petracic
  • Patent number: 7710756
    Abstract: A semiconductor device includes a magnetic wire having a plurality of magnetic domains, wherein the magnetic wire comprises a magnetic domain wall that is moved by either a pulse field or a pulse current. The magnetic wire of the semiconductor device does not require an additional notch since the magnetic wire includes a magnetic domain wall, the moving distance of which is controlled by a pulse field or a pulse current.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chee-kheng Lim, Yong-su Kim
  • Patent number: 7710766
    Abstract: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is preferably conducted through the application of a magnetic field and/or a mechanical action. The reading process is preferably conducted through atomic-force microscopy, magnetic-force microscopy, spin-polarized electrons, magneto-optical Kerr effect, optical interferometry or other methods, or other methods/effects. The multifunctionality (crystallographic, magnetic, and shape states each representing a functionality) of the multi-state elements allows for simultaneous operations including read&write, sense&indicate, and sense&control.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: May 4, 2010
    Assignee: Boise State University
    Inventors: Peter Mullner, William B. Knowlton
  • Patent number: 7710769
    Abstract: A serial magnetic mass storage device and associated data storage method is provided based on magnetic nanowires that support single magnetic domains separated by domain walls. Each data-storing nanowire has a plurality of crossing nanowires along its length, forming cross junctions that constitute domain wall pinning sites. Data is fed through each data-storing nanowire by moving the magnetic domains under the action of a field that alternates between alignment and anti-alignment with the crossing nanowires. The data is encoded in the chirality of the domain walls, with up and down chirality transverse domain walls being used to encode 0's and 1's. Data is clocked into each nanowire with suitable nucleation generators capable of nucleating domains with domain walls of pre-defined chirality. Data is clocked out of each nanowire with suitable magnetic field sensors that sense the chirality.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: May 4, 2010
    Assignee: Ingenia Holdings UK Limited
    Inventors: Russell Paul Cowburn, Dorothee Petit, Dan Read
  • Patent number: 7697323
    Abstract: A magnetic storage device is provided which has significantly reduced power consumption. The magnetic storage device includes: a yoke which is arranged so as to cover part of a line extending in an arbitrary direction; and a magneto-resistive element which is arranged near the line and is capable of writing information using a field occurring from the line. The magnetic storage device is set to satisfy the equation Iw?a·R+b, where Iw is the write current necessary for the line, R is the magnetoresistance of the yoke, a (mA·H)=7.5E?11, and b (mA)=0.1.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: April 13, 2010
    Assignee: TDK Corporation
    Inventors: Katsumichi Tagami, Keiji Koga, Tohru Oikawa
  • Patent number: 7668005
    Abstract: A magnetic memory includes a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and a word line electrically connected to the magnetoresistive elements. Data erase is performed by setting the magnetization direction of the free layer in a first direction by a magnetic field induced by a current flowing through the word line, and data of the magnetoresistive elements are erased by one time data erase. Data write is performed by setting the magnetization direction of the free layer in a second direction by spin-transfer magnetization reversal by supplying a current in one direction to the magnetoresistive elements.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: February 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda
  • Patent number: 7652913
    Abstract: It is made possible to cause spin inversion at a low current density which does not cause element destruction and to conduct writing with a small current. A magnetoresistance effect element includes: a magnetization pinned layer in which magnetization direction is pinned; a magnetic recording layer in which magnetization direction is changeable, the magnetization direction in the magnetization pinned layer forming an angle which is greater than 0 degree and less than 180 degrees with a magnetization direction in the magnetic recording layer, and the magnetization direction in the magnetic recording layer being inverted by injecting spin-polarized electrons into the magnetic recording layer; and a non-magnetic metal layer provided between the magnetization pinned layer and the magnetic recording layer.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Yoshiaki Saito, Tomoaki Inokuchi
  • Patent number: 7626857
    Abstract: Provided is a current induced switching magnetoresistance device comprising a magnetic multilayer composed of a first ferromagnetic layer, a nonferromagnetic layer, and a second ferromagnetic layer, wherein the first ferromagnetic layer has an upper electrode, the second ferromagnetic layer pinned by an antiferromagnet, wherein the antiferromagnet contains a lower electrode at its lower part, and the second ferromagnetic layer is embedded with a nano oxide layer. It is preferable to have at least a part of the lower electrode in contact with the second ferromagnetic layer. The magnetoresistance device provides a lower critical current (Ic) for the magnetization reversal and has an increased resistance.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: December 1, 2009
    Assignee: Korea Institute of Science and Technology
    Inventors: Kyung-Ho Shin, Nguyen Thi Hoang Yen, Hyun-Jung Yi
  • Patent number: 7619936
    Abstract: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 7613035
    Abstract: A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ1, MTJ2 and a select transistor connected to the connection node of the magnetoresistance effect elements MTJ1, MTJ2, a first signal line extended in a first direction and connected to the magnetoresistance effect element MTJ1, a second signal line extended in the first direction and connected to the magnetoresistance effect element MTJ2, and a third signal line extended in a second direction and crossing the first signal line in a region where the magnetoresistance effect element MTJ1 is formed and crossing the second signal line in a region where the magnetoresistance effect element MTJ2 is formed. When memory information is written into the memory cell, the memory information to be memorized is switched by directions of write currents to be flowed to the first and the second signal lines.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: November 3, 2009
    Assignee: Fujitsu Limited
    Inventor: Masaki Aoki
  • Patent number: RE41693
    Abstract: Excitation of a triad artificial photosynthetic reaction center consisting of a porphyrin (P) convalently linked to a fullerene electron acceptor (C60) and a carotenoid secondary donor (C) leads to the formation of a long-lived C+-P-C60? charge-separated state via photoinduced electron transfer. This reaction occurs in a frozen organic glass down to at least 8 K. At 77 K, charge recombination of C*+-P-C60? occurs on the ?s time scale, and yields solely the carotenoid triplet state. In the presence of a small (20 mT) static magnetic field, the lifetime of the charge-separated state is increased by 50%. This is ascribed to the effect of the magnetic field on interconversion of the singlet and triplet biradicals. At zero field, the initially formed singlet biradical state is in equilibrium with the three triplet biradical sublevels, and all four states have comparable populations. Decay to the carotenoid triplet only occurs from the three triplet sublevels.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 14, 2010
    Assignee: Arizona Board of Regents, Acting for and on Behalf of, Arizona State University
    Inventors: John D. Gust, Jr., Ana L. Moore, Thomas Moore