Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: Excitation of a triad artificial photosynthetic reaction center consisting of a porphyrin (P) convalently linked to a fullerene electron acceptor (C60) and a carotenoid secondary donor (C) leads to the formation of a long-lived C+-P-C60− charge-separated state via photoinduced electron transfer. This reaction occurs in a frozen organic glass down to at least 8 K. At 77 K, charge recombination of C*+-P-C60− occurs on the &mgr;s time scale, and yields solely the carotenoid triplet state. In the presence of a small (20 mT) static magnetic field, the lifetime of the charge-separated state is increased by 50%. This is ascribed to the effect of the magnetic field on interconversion of the singlet and triplet biradicals. At zero field, the initially formed singlet biradical state is in equilibrium with the three triplet biradical sublevels, and all four states have comparable populations. Decay to the carotenoid triplet only occurs from the three triplet sublevels.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

Abstract: A memory device having an array of resistive memory cells with row lines that are maintained at ground potential during quiescent operation of the device. During a read operation, one of the row lines is adapted to be coupled to a non-ground potential. Such coupling configures a memory cell of the array to be sensed in a voltage divider with a column line coupled to a common node of the voltage divider. An amplifier adapted to amplify a voltage detected on the column line is provided and additional circuitry is provided to translate the amplified voltage of the amplifier as a logic state of digital data stored in the device.

Abstract: A memory cell of a data storage device includes serially-connected first and second magnetoresistive devices. The first magnetoresistive device has first and second resistance states. The second magnetoresistive device has third and fourth resistance states. The four resistance states are detectably different.

Abstract: A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.

Abstract: The present disclosure relates to a magnetic memory device. In one embodiment, the magnetic memory device comprises a plurality of memory cells, and a plurality of write conductors adjacent the memory cells but electrically isolated from the memory cells, at least two of the write conductors being connected to a single shared switch, wherein the write conductors are configured to provide a path for current to flow to thereby generate magnetic fields used to change a state of the memory cells.

Abstract: A method of adaptively writing magnetic memory cells of a MRAM is disclosed according to an embodiment of the present invention. The method comprises providing a logical data block of a memory array having magnetic memory cells, each magnetic memory cell in a known initial state and each magnetic memory cell configured along an easy-axis magnetic field generating conductor and writing to the magnetic memory cells using a predefined minimum current level. The method may further comprise sensing the magnetic memory cells to determine if data has been successfully written, incrementing the current level if writing was unsuccessful and repeating above.

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position &thgr;1. The reticle is adjusted to a second rotational position &thgr;2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position &thgr;2. The second image is non-orthogonal with respect to the first image. Other aspects are provided herein.

Abstract: An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.

Abstract: A circuit is provided herein, which is adapted to supply different current magnitudes along opposing directions of a conductive line. Such a circuit may be particularly beneficial in compensating for the effects of unintentional magnetic coupling within MRAM devices. In addition, a method is provided herein for configuring a device having a magnetic memory array, which receives a first current magnitude along one direction and a substantially different current magnitude along an opposite direction of the magnetic memory array. Furthermore, a method is provided herein which assigns tunable current magnitudes for write operations along conductive lines of a memory circuit. Such tunable writing currents advantageously increase the write selectivity of the memory circuit. More specifically, the tunable writing currents compensate for ferromagnetic and antiferromagnetic coupling within magnetic memory cells caused by uneven surface topology and non-zero total magnetic moments, respectively.

Abstract: A nonvolatile storage device and method of operation capable of preventing opens in a word line and/or bit line that may result from electromigration is disclosed. A nonvolatile storage device according to an embodiment may include a number of magnetic resistance elements provided at intersections of word lines and bit lines, a word line control circuit for selecting one word line and supplying a write current thereto in a write operation, and a bit line control circuit for selecting one bit line and supplying a write current thereto. A word line control circuit can provide a bidirectional write current to a word line.

Abstract: A magnetic memory (400) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various criteria, such as a data value being programmed and a previous current direction are used to determine the direction of the write currents used in the word and bit lines during programming.

Abstract: A tunneling magnetoresistive storage unit (TMR unit) includes a hollow cylinder-shaped free-spin element having one open end, a columnlike fixed-spin element formed inside the cylinder-shaped free-spin element, and a thin insulator layer located between them. The spin direction in the fixed-spin element is fixed to a predefined circumferential direction of its column-shaped magnetic substance beforehand and a tunneling current is flowed between the free-spin element and the fixed-spin element. A rotating magnetic field produced as a consequence is used to set the spin direction in the cylinder-shaped free-spin element to one of its circumferential directions. This structure decreases the amount of electric current required for performing data write operation, also enabling miniaturization and a higher level of integration of the TMR unit and a magnetic random-access memory by employing such TMR units.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: A system and method for determining the logic state of a memory cell in a magnetic tunnel junction (MTJ) memory device based on the ratio of the current through the cell at different bias points are disclosed. A memory cell in an MJT memory device is sequentially subjected to at least two different bias voltages. The current through the cell at each of the bias voltages is measured, and a ratio of the different currents is determined. The ratio is then compared with a predetermined value to determine the logic state of the cell. The predetermined value can be a known value. Alternatively, the predetermined value can be determined by application of the system and method to a reference cell having a known logic state.

Abstract: A memory device having an array of resistive memory cells with row lines that are maintained at ground potential during quiescent operation of the device. During a read operation, one of the row lines is adapted to be coupled to a non-ground potential. Such coupling configures a memory cell of the array to be sensed in a voltage divider with a column line coupled to a common node of the voltage divider. An amplifier adapted to amplify a voltage detected on the column line is provided and additional circuitry is provided to translate the amplified voltage of the amplifier as a logic state of digital data stored in the device.

Abstract: An MRAM array includes a plurality of memory cells arranged in rows and columns are programmed, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line. According to one aspect of the present invention, a method for writing data to selected memory cells includes applying a row current to a selected word line and applying a first column current to a selected bit line. The column current is applied in a first direction. Second column currents are applied to at least the unselected bit lines adjacent the selected bit line. The second column currents are applied in a second direction that is opposite the first direction.

Abstract: A circuit for controlling a read operation for a magnetic random access memory (MRAM) comprising an array of magnetic tunnel junctions (MTJ) having conducting row and column lines attached thereto. The circuitry comprises a current supply for providing a read current, and a row selector for selecting a row containing a junction to be read and applying the read current to that row with the respective row line. An unselected row switch switches to at least some of the row lines not connected to the MTJ to be read, and a voltage source applies, via the unselected row switch, a voltage to each of the unselected row lines that is substantially identical in level to the voltage on the selected row line. A column selector selects the column line connected to the array containing the MTJ to be read, and a voltage detector for detecting the voltage across the MTJ to be read via the selected column and row lines.

Abstract: This invention presents a novel write line segmentation architecture for writing magnetoresitive random access memories (MRAM). Only the memory cells in a selected segment get a high hard axis field generated by a write line current. Memory cells of deselected segments do not receive this hard axis field. This prevents an undesired state change in particularly sensitive memory cells.

Abstract: An information recording and reproducing method for a magnetic memory including a variable resistor having a first magnetic layer for storing information on a basis of a direction of magnetization, a non-magnetic layer, and a second magnetic layer having a coercive force that is smaller than a coercive force of the first magnetic layer, the variable resistor exhibiting different resistances according to magnetization directions of the first magnetic layer and the second magnetic layer, the information recording and reproducing method including the steps of: initializing the second magnetic layer in a first magnetization direction; detecting a resistance value of the variable resistor and holding the detected resistance value as a first resistance value; detecting a second resistance value by reversing magnetization of the second magnetization layer in a second magnetization direction and comparing the first resistance value with the second resistance value; and reproducing information according to a result of

Abstract: A magnetic layer (46) of a magnetoelectronics element (40) is provided that has a first sub-element layer (48) and a second sub-element layer (50). The first sub-element layer (48) is configured to have a first area and the second sub-element layer (50) is configured to have a second area that is less than the first area.

Abstract: A circuit for controlling a read operation for a magnetic random access memory (MRAM) comprising an array of magnetic tunnel junctions (MTJ) having conducting row and column lines attached thereto. The circuitry comprises a current supply for providing a read current, and a row selector for selecting a row containing a junction to be read and applying the read current to that row with the respective row line. An unselected row switch switches to at least some of the row lines not connected to the MTJ to be read, and a voltage source applies, via the unselected row switch, a voltage to each of the unselected row lines that is substantially identical in level to the voltage on the selected row line. A column selector selects the column line connected to the array containing the MTJ to be read, and a voltage detector for detecting the voltage across the MTJ to be read via the selected column and row lines.

Abstract: A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of ‘1’s and ‘0’s, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the ‘1’s and ‘0’s are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

Abstract: A method for preventing electromigration in a magnetic random access memory (MRAM) is described. In the method, after a programming step, a signal which compensates for the electromigration and has opposite polarity is fed to the wordline and bitline in such a way that programming does not occur in the memory cells.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2)(1+Rmin/Rmax), where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell. A reference voltage generator is disclosed which generates the reference voltage and includes an operational amplifier and two MTJ memory cells connected to provide an output signal equal to (Vbias1/2)(1+Rmin/Rmax).

Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing.

Abstract: In a storage device having a read buffer for storing datum read out from a storage medium in the form of cache data, datum are sequentially stored in the read buffer, but the read buffer is not partitioned into a plurality of areas. In the event that a plurality of cache data areas, each of which is an assembly of datum continued in an address on the storage medium, exist in the read buffer, a weighting is applied for each cache data area in connection with an importance of a data save. An overwrite is performed on an area of the minimum weight, and at least data on an area of the maximum weight is saved.

Abstract: A method for manufacturing a semiconductor device capable of performing a writing operation with a small amount of current by forming a thin oxide film on the surface a word line being used as a write line so as to reduce the distance between an MTJ cell and the word line includes the steps of forming a word line on a semiconductor substrate, wherein the word line is used as a write line, forming a planarized layer insulating film exposing the surface of the word line, forming a dielectric film on the surface of the word line, forming a seed layer connected to the word line through the dielectric film and configuring a cell on the top of the seed layer and in an upper portion of the word line.

Abstract: A magnetic random access memory or the like has a plurality of magnetic storage elements laminated on a single transistor, resulting in a reduction in the number of necessary components and a considerable enhancement in the degree of integration of the memory.

Abstract: The invention described herein defines a system and a method for selectively controlling the sensitivity of a region of a magnetoresistive element to an incident magnetic field, by applying an external magnetic field to the magnetoresistive element. A number of applications to non-volatile data storage are described, as is a magnetic sweep element based on a FET structure. Finally, the storage media and recording modes (in-plane vs. perpendicular) best suited to the proposed applications are analyzed, and the desired or optimal characteristics of the proposed devices are discussed.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2) (1+Rmin/Rmax) where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell.

Abstract: A data carrier (DC) has a receiving-means configuration (RC) which includes a switching means (S) and a first transmission coil (L1), which can be short-circuited with the aid of the switching means (S), and at least one second transmission coil (L2 ), which is arranged in series with the first transmission coil (L1), and capacitor configuration (CC), which is arranged in parallel with at least the second transmission coil (L2), the receiving means configuration (RC) being configured to be controllable as regards the value of at least one of its elements comprising the at least one second transmission coil (L2) and the capacitor configuration (CC).

Abstract: An architecture for selectively writing one or more magnetic memory cells in a magnetic random access memory (MRAM) device comprises at least one write line including a global write line conductor and a plurality of segmented write line conductors connected thereto, the global write line conductor being substantially isolated from the memory cells.

Abstract: A system and method for programming a magnetoresistive memory array by applying current on a memory line aligned along the easy axis of the memory array, where the current generates a magnetic field that is independently sufficient to program at least two multi-state magnetoresistive memory elements coupled along the memory line. The memory array may be organized as one or more column memory lines along the easy axis and one or more row memory lines along a hard axis. In this configuration, the column drive circuitry includes a current source for each column memory line that is capable of programming all of the memory elements along the respective column memory line. Each column current source may assert a lesser or medium current level that generates a magnetic field that is insufficient alone to program the logic state of any memory element in the memory array.

Abstract: A stabilized magnetic memory cell including a data storage layer having an interior region and a pair of end regions near a pair of opposing edges of the data storage layer and a stabilizing material that pins a magnetization in the end regions to a predetermined direction. A method for stabilizing a magnetic memory cell includes the steps of applying a magnetic field that rotates a magnetization in a pair of opposing side regions of a data storage layer of the magnetic memory cell toward a predetermined direction and that reduces free poles in a pair of opposing end regions of the magnetic memory cell, thereby reducing the likelihood of unpredictable switching behavior in the end regions.

Abstract: Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).

Abstract: Disclosed are apparatus and methods for efficiently writing states to one or more magneto-resistive elements. In one embodiment, current switches are provided for directing a write current through a number of write lines to control the write state of the magneto-resistive elements. In another embodiment, a sense current is selectively controlled to control which magneto-resistive elements are written to a particular state. In both embodiments, a latching element may be used to sense the state of the magneto-resistive elements, and may assume a corresponding logic state.