Abstract: There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract: A method for resetting a spin-transfer based random access memory system, the method comprising, inducing a first current through a first conductor, wherein the first current is operative to propagate a magnetic domain wall in a ferromagnetic film layer and the propagation of the magnetic domain wall is further operative to change the direction of a magnetic state of a first free layer magnet, and inducing a second current only through a second conductor, wherein the second current is operative to further propagate the magnetic domain wall in the ferromagnetic film layer and the propagation of the magnetic domain wall is further operative to change the direction of a magnetic state of a second free layer magnet.

Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.

Abstract: An exemplary magnetic random access memory system comprising, a spin-current generating portion including, a ferromagnetic film layer, and a conductance layer, a first write portion in electrical contact with the ferromagnetic film including, a selection device, and a first read portion in electrical contact with the conductance layer including, a free layer magnet, a read non-magnetic layer, and a reference layer, a second write portion in electrical contact with the ferromagnetic film, and a second read portion in electrical contact with the conductance layer.

Abstract: A magnetic memory cell is provided. The memory cell includes a metal device, a first word line, and a second word line. The metal device includes a first magnetic layer having a first dipole; a second magnetic layer having a second dipole; and an conductive layer located between the first and second magnetic layers. The first word line is positioned near the first magnetic layer to change the direction of the first dipole. The second word line is positioned near the second magnetic layer to change the direction of the second dipole. A method of reading/writing a bit in the magnetic memory cell is also provided.

Abstract: A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.

Abstract: A programmable system for storage of one-time programmable information comprises an interface translator and a one-time programmable device. The interface translator receives and translates a command code to program code comprising a sequence of write instructions and a designated data block. The one-time programmable device is coupled to the interface translator, programmed by the write instructions to store the designated data block. The one-time programmable device can only be programmed once, such that the designated data block being stored is fully protected.

Abstract: This invention relates to a device comprising at least a first ferromagnetic layer (202) and an element (204) exchange-bias coupled to this layer in at least one place through an interface (208), for controlling the magnetic state of the ferromagnetic layer (202) in the coupling place with an electrical field applied at least on the element, the element comprising a material with clamped antiferromagnetic and ferroelectric characteristics.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of magnetic memory elements, a control line group and a read driving circuit.

Abstract: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.

Abstract: A solid state magnetic memory system and method disposes an array of magnetic media cells in an array on a substrate. In an exemplary embodiment, drive electronics are fabricated into the substrate through conventional CMOS processing in alignment with associated cells of the array. The magnetic media cells each include a magnetic media bit and a magnetoresistive or GMR stack for reading the state of the media bit. Addressing lines are juxtaposed with the media bits to permit programming and erasing of selected ones of the bits. In at least some embodiments, sector erase may be performed.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular to the first metal lines. The plurality of second metal lines each has a tunnel through which the plurality of first metal lines pass. First input units are connected to the plurality of first metal lines and supply a current to drag or move the plurality of magnetic domains. Second input units are connected to the plurality of second metal lines to supply a current for switching the magnetization directions of magnetic domains inside the tunnels. Sensing units are connected to the plurality of second metal lines for sensing an electromotive force caused by magnetic domain walls passing through the tunnels.

Abstract: A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the memory cells that can be read only during a power up initialization. The second part of the array is used to store configuration data for altering the physical operation of the memory array. Programmable current sources and timing delays use the stored configuration data to optimize device performance. A redundant section of memory cells is activated by the configuration data.

Abstract: A magnetoresistance effect element includes a first ferromagnetic layer (1), insulating layer (3) overlying the first ferromagnetic layer, and second ferromagnetic layer (2) overlying the insulating layer. The insulating layer has formed a through hole (A) having an opening width not larger than 20 nm, and the first and second ferromagnetic layers are connected to each other via the through hole.

Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.

Abstract: The invention concerns a magnetic memory, whereof each memory point consists of a magnetic tunnel junction (60), comprising: a magnetic layer, called trapped layer (61), whereof the magnetization is rigid; a magnetic layer, called free layer (63), whereof the magnetization may be inverse; and insulating layer (62), interposed between the free layer (73) and the trapped layer (71) and respectively in contact with said two layers. The free layer (63) is made with an amorphous or nanocrytallized alloy based on rare earth or a transition metal, the magnetic order of said alloy being of the ferromagnetic type, said free layer having a substantially planar magnetization.

Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat??sat)?(Hsw+?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.

Abstract: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

Abstract: A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.

Abstract: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to apply, to the control gate of the cell transistor in read, a potential of the same sign as that of a potential applied to the gate of the selector gate transistor.

Abstract: Disclosed herein are a magnetic memory device and method for storing and retrieving data. The magnetic memory device includes a read disk and a storage disk. The read disk comprises of an array of read heads wherein the individual read head corresponds to a storage element on the storage disk.

Abstract: A method and system for providing a magnetic memory device are disclosed. The method and system include providing a magnetic element that includes a data storage layer having at least one easy axis in at least a first direction. The method and system also include providing a hard bias structure surrounding a portion of the magnetic element. The hard bias structure is also configured to provide at least one hard bias field essentially parallel to the at least the first direction or essentially perpendicular to the at least the first direction.

Abstract: In a magnetic random access memory (MRAM), setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.

Abstract: The word line segment select transistor of a segmented word line array is placed on the word line current source side. This eliminates many undesirable effects currently associated with segmented word line MRAM arrays.

Abstract: The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be used to control and switch the magnetization direction of a magnetic region in such a device. The magnetic device comprises a pinned magnetic layer with a fixed magnetization direction, a free magnetic layer with a free magnetization direction, and a read-out magnetic layer with a fixed magnetization direction. The pinned magnetic layer and the free magnetic layer are separated by a non-magnetic layer, and the free magnetic layer and the read-out magnetic layer are separated by another non-magnetic layer. The magnetization directions of the pinned and free layers generally do not point along the same axis. The non-magnetic layers minimize the magnetic interaction between the magnetic layers.

Abstract: An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a non-magnetic tunneling barrier layer. The first magnetic region includes a reference layer having a fixed magnetization adjacent the tunneling barrier layer. The second magnetic region includes a free layer having first and second free magnetizations aligned with an easy axis of magnetization of the free layer. The first and second free magnetizations are oppositely aligned and separated by a magnetic domain wall. The magnetic domain wall is magnetically movable along the easy axis of the free layer, and the free layer is magnetically coupled to magnetic fields generated by first and second currents running through first and second conductive lines crossing each other, wherein the easy axis of the free layer is inclined under an inclination angle relative to both the first and second conductive lines.

Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

Abstract: The invention relates to a magnetic memory with write inhibit selection and the writing method for same. Each memory element of the invention comprises a magnetic tunnel junction (70) consisting of: a magnetic layer, known as the trapped layer (71), having hard magnetisation; a magnetic layer, known as the free layer (73), the magnetisation of which may be reversed; and an insulating layer (72) which is disposed between the free layer (73) and the trapped layer (71) and which is in contact with both of said layers. The free layer (73) is made from an amorphous or nanocrystalline alloy based on rare earth and a transition metal, the magnetic order of said alloy being of the ferrimagnetic type. The selected operating temperature of the inventive memory is close to the compensation temperature of the alloy.

Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat?N?sat)?(Hsw+N?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

Abstract: A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.

Abstract: A memory storage circuit is provided which includes a plurality of magnetic elements each configured to store bits in a first or a second logic state. The storage circuit may further include a plurality of transistors coupled to at least two of the magnetic elements. Such a plurality of transistors may be collectively configured to store bits in the first and second logic states as well. The memory storage circuit may include circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors. Another circuit is provided which includes a magnetic element interposed between a bit line and an electrode. The circuit may further include a first set of circuitry configured to induce current flow through the magnetic element in a direction from the electrode to the bit line. A method for operating a memory storage circuit with the aforementioned configurations is also provided.

Abstract: A word current source (445) for a magnetoresistive random access memory circuit (420) includes an n-channel transistor (430) including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the magnetoresistive random access memory circuit. A positive supply voltage is coupled to the magnetoresistive random access memory circuit (420) so as to allow current to flow through the magnetoresistive random access memory circuit (420) when an activation signal is applied to the gate by the control circuit.

Abstract: In a magnetic random access memory (MRAM), setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.

Abstract: A method and system for providing a magnetic element capable of storing multiple bits is disclosed. The method and system include providing first pinned layer, a first nonmagnetic layer, a first free layer, a connecting layer, a second pinned layer, a second nonmagetic layer and a second free layer. The first pinned layer is ferromagnetic and has a first pinned layer magnetization pinned in a first direction. The first nonmagnetic layer resides between the first pinned layer and the first free layer. The first free layer being ferromagnetic and has a first free layer magnetization. The second pinned layer is ferromagnetic and has a second pinned layer magnetization pinned in a second direction. The connecting layer resides between the second pinned layer and the first free layer. The second nonmagnetic layer resides between the second pinned layer and the second free layer. The second free layer being ferromagnetic and having a second free layer magnetization.

Abstract: The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be used to control and switch the magnetization direction of a magnetic region in such a device. The magnetic device comprises a pinned magnetic layer with a fixed magnetization direction, a free magnetic layer with a free magnetization direction, and a read-out magnetic layer with a fixed magnetization direction. The pinned magnetic layer and the free magnetic layer are separated by a non-magnetic layer, and the free magnetic layer and the read-out magnetic layer are separated by another non-magnetic layer. The magnetization directions of the pinned and free layers generally do not point along the same axis. The non-magnetic layers minimize the magnetic interaction between the magnetic layers.

Abstract: A sensor for a magnetic random-access memory (MRAM) of an embodiment of the invention includes an amplifier having at least two inputs and at least two outputs. The inputs are coupled to a magnetic storage element of the MRAM having a resistance corresponding to a value stored thereby and the outputs provide an output voltage corresponding to the resistance of the magnetic storage element. The sensor comprises a chopper switch coupled between one input of the amplifier and the magnetic storage element, a chopper switch coupled between another input of the amplifier and the magnetic storage element, and a chopper switch coupled between the outputs of the amplifier.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

Abstract: A magnetic memory device can information with a low power consumption by inhibiting the coercive force from being increased by a demagnetizing field in a free layer, regardless of the thickness, moment, and the like of the free layer, even when the size of a magnetoresistive element is reduced.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate comprising a first region extending along the edge and a second region surrounded by the first region. Memory cell arrays are provided in the second region, and comprising a plurality of cells having an MTJ element. Gate transistors are provided in the first region, and have a current path having a first terminal connected with a bit line, which is a signal read path from the cells, and a second terminal opposite to the first terminal. Data buses are connected with the same number of the second terminals. A connection control circuit is provided in the second region, and connects selected two of the data buses to first and second output terminals, respectively. An amplifier circuit is provided in the first region, and amplifies a potential difference in accordance with signals outputted from the first and second output terminals.

Abstract: An information storage portion which stores tuning information is constituted by a plurality of magnetic elements & latch circuits. Each of the magnetic elements & latch circuits has two magneto-resistive effect elements, and the tuning information is stored in these elements. Complementary data are stored in the two magneto-resistive effect elements. After turning on a power supply, a power-on detection circuit outputs a transfer signal and a latch signal. When the transfer signal becomes “H”, the tuning information is transferred to the latch circuit. When the latch signal becomes “H”, the tuning information is latched to the latch circuit and supplied to the internal circuit.

Abstract: A magnetic tunneling junction (MTJ) memory cell for a magnetic random access memory (MRAM) array is formed as a chain of magnetostatically coupled segments. The segments can be circular, elliptical, lozenge shaped or shaped in other geometrical forms. Unlike the isolated cells of typical MTJ designs which exhibit curling of the magnetization at the cell ends and uncompensated pole structures, the present multi-segmented design, with the segments being magnetostatically coupled, undergoes magnetization switching at controlled nucleation sites by the fanning mode. As a result, the multi-segmented cells of the present invention are not subject to variations in switching fields due to shape irregularities and structural defects.

Abstract: A magnetic storage element capable of recording with a small magnetic field and retaining information stably and a recording method thereof, and a magnetic storage device having the magnetic storage element and capable of simplifying a drive circuit thereof are provided. The magnetic storage element comprises a storage layer, a non-magnetic layer and a pinned layer. The storage layer is composed of directly stacked first magnetic layer mainly composed of a transition metal and second magnetic layer mainly composed of a rare-earth metal; and a magnetization amount of the first magnetic layer is smaller than that of the second magnetic layer at a room temperature. A magnetization state of one direction is recorded by heating and applying a magnetic field to the storage layer, and a magnetization state of the other direction is recorded by making magnetic coupling work between the first magnetic layer and the pinned layer by heating.

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and providing at least one magnetic write line coupled with the plurality of magnetic memory cells. Each of the magnetic memory cells includes a magnetic element having a data storage layer. The data storage layer stores data magnetically. The magnetic write line(s) are magnetostatically coupled with at least the data storage layer of the magnetic element of the corresponding magnetic memory cells. Consequently, flux closure is substantially achieved for the data storage layer of each of the plurality of magnetic memory cells.