Having Fuse Element Patents (Class 365/225.7)
  • Notebook computer
    Patent number: 8531831
    Abstract: A notebook computer comprises a first machinery, a first latch, a second machinery, a slider, an elastic element and a push element. The first latch is disposed on an edge of the first machinery. The second machinery has one side pivotally connected to the first machinery, and the other side formed with at least one latching hole. When the computer is closed, the first latch is inserted into the latching hole. The slider includes a body and a second latch. The body is slidably disposed in the second machinery along a first moving path. The second latch, disposed on the body, suits to latch or unlatch the first latch. The elastic element has one end connected to the slider, and the other end connected to the second machinery. The push element, slidably disposed in the second machinery along a second moving path, suits to push the body.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventors: Chia-Ju Ho, Chih-Chin Yu
  • Notebook computer
    Patent number: 8531830
    Abstract: A notebook computer comprises a first machinery, a first latch, a second machinery, a slider, a second elastic element and a push element. The second machinery has one side pivotally connected to the first machinery, and the other side formed with at least one latching hole. The slider comprises a body, a second latch and a first elastic element. The body is slidably disposed in the second machinery along a first moving path. The second latch disposed on the body latches or unlatches the first latch disposed on the first machinery. The first elastic element has one end connected to the body, and the other end pressing the first latch. The second elastic element has one end connected to the slider, and the other end connected to the second machinery. The push element, slidably disposed in the second machinery along a second moving path, pushes the first elastic element.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventor: Chia-Ju Ho
  • Anti-fuse circuit
    Patent number: 8526244
    Abstract: An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 3, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Ming-Chien Huang
  • Test mode initialization device and method
    Patent number: 8514643
    Abstract: A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Hermann Wienchol
  • Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    Patent number: 8514648
    Abstract: Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Doo-Young Kim, Hyoung-Joo Kim, Ju-Seop Park
  • Semiconductor memory device
    Patent number: 8514642
    Abstract: A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but by using a non-volatile memory, which is provided in a memory controller, to store address data of a defective memory cell. The memory controller storing the address data of a defective memory cell contributes an increase in process speed, because it is not necessary to access the memory cell array in order to obtain the address data of the defective memory cell.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Fuse set and semiconductor integrated circuit apparatus having the same
    Patent number: 8509022
    Abstract: A fuse set includes a first row constituted by a plurality of fuses which are arranged with a first spacing; a second row including a plurality of fuses which are disposed to correspond to the fuses of the first row on the same plane, and separated from the fuses of the first row with a second spacing; and a connection part disposed between the first row and the second row and electrically connected with the plurality of fuses of the first row and the plurality of fuses of the second row, wherein the connection part and the pluralities of fuses of the first and second rows are disposed on different planes.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: August 13, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jong Jin Lee
  • Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
    Patent number: 8508971
    Abstract: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: August 13, 2013
    Assignee: Wafertech, LLC
    Inventors: Re-Long Chiu, Shu-Lan Ying, Wen-Szu Chung
  • Built-in self test for one-time-programmable memory
    Patent number: 8508972
    Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Analog Devices, Inc.
    Inventors: James M. Lee, Howard R. Samuels, Thomas W. Kelly
  • Method and system for split threshold voltage programmable bitcells
    Patent number: 8509023
    Abstract: A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: August 13, 2013
    Assignee: Broadcom Corporation
    Inventor: Jonathan Schmitt
  • Refresh control circuit and semiconductor memory apparatus using the same
    Patent number: 8493809
    Abstract: A refresh control circuit is capable of activating a plurality of bank selection signals in response to a refresh command signal. Each of the plurality of bank selection signals is assigned to one of a plurality of bank groups. The refresh control circuit is configured to activate the plurality of bank selection signals when a refresh cycle selection signal is deactivated, and activate a part of the plurality of bank selection signals when the refresh cycle selection signal is activated.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 23, 2013
    Assignee: SK Hynix Inc.
    Inventor: Ki Hoon Lee
  • MEMORY CELL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
    Publication number: 20130182518
    Abstract: A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage.
    Type: Application
    Filed: May 1, 2012
    Publication date: July 18, 2013
    Inventors: Tae-Hoon KIM, Sung-Mook Kim
  • Process variability tolerant programmable memory controller for a pipelined memory system
    Patent number: 8488405
    Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: July 16, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian, Raguram Damodaran
  • Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit
    Patent number: 8487646
    Abstract: In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: July 16, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Giao Minh Pham
  • METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
    Publication number: 20130176805
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Semiconductor device having resistance based memory array, method of reading, and systems associated therewith
    Patent number: 8482994
    Abstract: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Jin Lee, Du Eung Kim, Yong Jun Lee
  • Semiconductor device including fuse array and method of operation the same
    Patent number: 8482989
    Abstract: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-pil Son, Seong-jin Jang, Byung-sik Moon, Ju-seop Park
  • Antifuse unit cell of nonvolatile memory device for enhancing data sense margin and nonvolatile memory device with the same
    Patent number: 8483002
    Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 9, 2013
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon, Youn-Jang Kim
  • Fuse circuit and memory device including the same
    Patent number: 8477521
    Abstract: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwi-Dong Kim, Jun-Gi Choi
  • Redundancy control circuit and memory device including the same
    Patent number: 8472269
    Abstract: A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-Chul Kim
  • Anti-fuse circuit and integrated circuit including the same
    Patent number: 8472234
    Abstract: An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the occurrence of an anti-breakdown phenomenon. The anti-fuse circuit includes an anti-fuse, a breakdown of which occurs by a program voltage, configured to be electrically short-circuited, a read controller configured to be controlled by a read voltage received through the anti-fuse so as to output a short-circuiting status of the anti-fuse, and a switching unit configured to form a path that prevents a current flowing through the anti-fuse from being applied to the read controller during a program operation and prevents a current from flowing in the anti-fuse during a read operation.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 25, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keon Yoo
  • Repairing circuit for memory circuit and method thereof and memory circuit using the same
    Patent number: 8472265
    Abstract: A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 25, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Jen-Shou Hsu
  • Apparatus and method for testing one-time-programmable memory
    Patent number: 8472270
    Abstract: An apparatus and method of testing one-time-programmable memory limits current through a one-time-programmable memory to less than a threshold amplitude, where the memory has a fuse configured to blow upon receipt of a signal having the threshold amplitude. The method also uses blow signal assertion circuitry to attempt to assert a blow signal to the fuse. When not defective, blow signal assertion circuitry is configured to permit the low amplitude signal to flow through the fuse when the fuse is not blown and the blow signal is asserted. The method then produces an output signal having a success value if the limited current flows through the fuse, and a failure value if the current does not flow through the fuse.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Howard R. Samuels, Thomas W. Kelly
  • ELECTRICAL FUSE MEMORY
    Publication number: 20130155799
    Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
    Type: Application
    Filed: February 20, 2013
    Publication date: June 20, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sung-Chieh LIN, David YEN, Wei-Li LIAO, Jiann-Tseng HUANG, Kuoyuan (Peter) HSU
  • Structure and method for storing multiple repair pass data into a fusebay
    Patent number: 8467260
    Abstract: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Michael R. Ouellette, Michael A. Ziegerhofer
  • Integrated circuits with nonvolatile memory elements
    Patent number: 8467240
    Abstract: Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 18, 2013
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Integrated circuit self aligned 3D memory array and manufacturing method
    Patent number: 8467219
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 18, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Multi-time programmable memory
    Patent number: 8462575
    Abstract: Multi-time programmable memory elements are disclosed. The disclosed memory elements extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmability. The disclosed memory elements significantly reduce area requirements and control circuitry complexity of memory elements. The disclosed memory elements can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 11, 2013
    Assignee: Broadcom Corporation
    Inventor: Myron Buer
  • Memory address repair without enable fuses
    Patent number: 8462570
    Abstract: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Greg Blodgett
  • Semiconductor device
    Patent number: 8456884
    Abstract: Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRB1 and TRB2) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRB1 and TRB2), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit 5 (and a word line drive circuit 4).
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 4, 2013
    Assignee: Sony Corporation
    Inventor: Yuji Torige
  • Semiconductor memory apparatus, memory system, and programming method thereof
    Patent number: 8437212
    Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 7, 2013
    Assignee: SK Hynix Inc.
    Inventor: Kie Bong Ku
  • Integrated circuit
    Patent number: 8432763
    Abstract: An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jinyeong Moon
  • Measuring electrical resistance
    Patent number: 8432759
    Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuoyuan Hsu, Po-Hung Chen, Jiann-Tseng Huang, Subramani Kengeri
  • ELECTRICAL FUSE MEMORY ARRAYS
    Publication number: 20130100756
    Abstract: A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resisivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
    Type: Application
    Filed: October 21, 2011
    Publication date: April 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Li LIAO, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • Redundancy memory cell access circuit and semiconductor memory device including the same
    Patent number: 8427893
    Abstract: A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eunsung Seo
  • Semiconductor device having nonvolatile memory element and manufacturing method thereof
    Patent number: 8422327
    Abstract: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: April 16, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuhiro Teramoto, Hiroki Fujisawa, Susumu Takahashi
  • Semiconductor memory apparatus, and circuit and method for controlling faulty address therein
    Patent number: 8416637
    Abstract: A faulty address control circuit comprises a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current; a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and an address storage and determination unit configured to receive the address signal, be driven by the driving signal to output the address signal or an inverted signal of the address signal.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 9, 2013
    Assignee: SK Hynix Inc.
    Inventor: Woo Jin Rim
  • Multi-chip package and method of operating the same
    Patent number: 8416639
    Abstract: A multi-chip package includes a plurality of memory chips for performing a content addressable memory (CAM) read operation in response to a command signal for the CAM read operation and an address signal for selecting the memory chips and a controller for outputting the command signal and the address signal to the memory chips and controlling the sequence of the CAM read operations for the memory chips.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 9, 2013
    Assignee: SK Hynix Inc.
    Inventor: Won Kyung Kang
  • Semiconductor device capable of adjusting memory page size based on a row address and a bank address
    Patent number: 8411528
    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Lee, Uk Song Kang, Hoe Ju Chung
  • Programmable read only memory
    Patent number: 8411482
    Abstract: A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Zhanping Chen, Sarvesh Kulkarni, Kevin Zhang
  • Capacitive discharge fuse programming apparatus and method
    Patent number: 8405448
    Abstract: An apparatus for programming a fuse includes a programmable branch comprising a fusable element and a reverse-biased diode connected in series. The programmable branch is connected in parallel with a current boost capacitor. An electrical source or input supplies a current that is sufficient to charge the current boost capacitor to a breakdown voltage of the reverse-biased diode and subsequently melt the reverse-biased diode. Melting the reverse-biased diode may induce a reduction in voltage across the current boost capacitor and result in a current surge through the programmable branch that is sufficient to program (i.e. blow) the fusable element. A corresponding method for programming a fuse is also disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 26, 2013
    Inventors: David R. Hall, Marshall Soares, Paul Moody
  • Electrical fuse memory
    Patent number: 8400860
    Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
  • Antifuse programmable memory array
    Patent number: 8395923
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: March 12, 2013
    Assignee: Intel Corporation
    Inventors: Zhanping Chen, Sarvesh H. Kulkarni, Kevin Zhang
  • Semiconductor memory device with a skew signal generator for adjusting a delay interval of internal circuitry
    Patent number: 8395952
    Abstract: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Youn Lee, Ho Uk Song
  • Method and Apparatus for Programming an Anti-Fuse Element in a High-Voltage Integrated Circuit
    Publication number: 20130058182
    Abstract: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device.
    Type: Application
    Filed: October 19, 2012
    Publication date: March 7, 2013
    Applicant: POWER INTEGRATIONS, INC.
    Inventor: POWER INTEGRATIONS, INC.
  • Anti-fuse circuit and method for anti-fuse programming and test thereof
    Patent number: 8391091
    Abstract: An anti-fuse circuit including a plurality of programmable units and a test module is provided. The programmable units receive a stress voltage, a program data, and a write enable signal. During a programming period, the programmable units sequentially transmit the program data. When the write enable signal is enabled, the stress voltage stresses the programmable units according to the program data, and the programmable units output programming results for test. The test module is coupled to the programmable units and receives the program data and the programming results. During a test period, the test module compares the programming results with the program data and outputs different logic levels according to a result of the comparison of the first programming results and the program data. A method for anti-fuse programming and test adapted to the foregoing anti-fuse circuit is also provided.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: March 5, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Chien-Yi Chang, Ming-Chien Huang
  • SEMICONDUCTOR DEVICE HAVING REDUNDANT WORD LINES AND REDUNDANT BIT LINES
    Publication number: 20130051160
    Abstract: Disclosed herein is a device that includes a memory cell array having short and long sides, a row decoder, a row fuse circuit, a column decoder and a column fuse circuit. The row decoder, the row fuse circuit and the column fuse circuit are arranged along the long side of the memory cell array. The column decoder is arranged along the short side of the memory cell array.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 28, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Tatsuo SAWADA
  • Trim circuit and semiconductor memory device comprising same
    Patent number: 8379460
    Abstract: A trim circuit comprises a trim code storage unit, a global latch unit and a local latch unit. The trim code storage unit stores a plurality of trim codes and outputs a sensing code in response to an address signal. The global latch unit latches a calibrated code or the sensing code to generate a global output signal. The calibrated code is generated by performing a calibration on the sensing code. The local latch unit repeatedly latches the global output signal in response to the address signal to generate a plurality of trim output signals.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Yong Jeong
  • STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY
    Publication number: 20130033951
    Abstract: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin W. Gorman, Michael R. Ouellette, Michael A. Ziegerhofer
  • Semiconductor memory device and method of testing a sense amplifier of the same
    Patent number: 8369167
    Abstract: A semiconductor device includes the following elements. A sense amplifier amplifies signal on a bit line. A column switch is between the bit line and a local input-output line. A sub-amplifier amplifies signal on the local input-output line. A write switch is between the local input-output line and a main input-output line. A write amplifier amplifies write data and supplies the amplified write data to the main input-output line when data write operation is performed. A test circuit activates the sense amplifier while the test circuit deactivating the sub-amplifier and the write amplifier when a data read operation is performed in test mode. The test circuit places the column switch and the write switch in conductive state.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: February 5, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Tomohiro Sawada