Combined Random And Sequential Addressing Patents (Class 365/230.09)
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Patent number: 7539077Abstract: A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.Type: GrantFiled: July 11, 2007Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Weon Yoon, Heung-Soo Lim
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Patent number: 7499372Abstract: When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.Type: GrantFiled: May 26, 2006Date of Patent: March 3, 2009Assignee: Seiko Epson CorporationInventors: Noboru Asauchi, Eitaro Otsuka
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Patent number: 7495993Abstract: A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circuit to realize savings in power and silicon area. Because random access to the semiconductor device is not required, the interface from external to the semiconductor device is also simplified by eliminating at least the address port that is used to specify the memory locations accessed. The method is applicable not only to non-volatile memory technologies (e.g., flash memory), it is also applicable to volatile memory technologies, such as transient charge storage-based memory circuits (e.g., DRAMs) and metastable states-based memory circuits (e.g., SRAMs).Type: GrantFiled: October 25, 2006Date of Patent: February 24, 2009Assignee: Capso Vision, Inc.Inventor: Kang-Huai Wang
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Patent number: 7489583Abstract: Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention.Type: GrantFiled: September 6, 2005Date of Patent: February 10, 2009Inventors: Philip J. Kuekes, J. Warren Roblnett, Ron M. Roth, Gadlel Seroussl, Gregory S. Smider, R. Stanley Williams
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Patent number: 7457185Abstract: A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank; and a bank refresh block for supporting a refresh operation performed in sequence to each bank in response to the refresh information of each bank.Type: GrantFiled: September 22, 2006Date of Patent: November 25, 2008Assignee: Hynix Semiconductor Inc.Inventor: Jee-Yul Kim
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Patent number: 7436689Abstract: When an address storing/comparing circuit stores no address identical to an external input address in read operation, in a main memory read data is written back to a data storing area after data read therefrom, and data indicating a sum of a predetermined value and a value of the read data is written to a history storing area after data read therefrom. In a sub memory, after data read from a history storing area, data read from the data storing area of the main memory is written to a data storing area and the data indicating the sum of the predetermined value and the value of the data read from the history storing area of the main memory is written to the history storing area, when the value of the data read from the history storing area of the main memory is larger than that of the sub memory.Type: GrantFiled: December 27, 2006Date of Patent: October 14, 2008Assignee: Fujitsu LimitedInventor: Isao Fukushi
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Patent number: 7433258Abstract: A method and architecture that overcomes the problem of latency-caused performance degradation of electronic memory systems. The method involves a “Posted Precharge,” by which an external command for Precharge is given as early as possible, such as immediately following a Read command. The execution of the Precharge is delayed by a precharge counter until all Read/Write commands are completed. By posting a precharge command on a bus at the first available opportunity, multiple pages can be open on the same bank of a memory device. As a result, access latencies are significantly reduced and efficiency of bus in electronic memory systems is significantly improved.Type: GrantFiled: October 8, 2004Date of Patent: October 7, 2008Assignee: DataSecure LLC.Inventors: G. R. Mohan Rao, Franz Michael Schuette
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Publication number: 20080198655Abstract: A memory device comprises a plurality of memory cells, each of which comprising a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, wherein the memory cells are grouped into memory cell groups, each memory cell group defining a memory cell group area and being configured such that corresponding first electrodes are individually addressable, and corresponding second electrodes are commonly addressable via a common select device provided within the memory cell group area of the memory cell group.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Inventor: Jan Keller
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Patent number: 7352648Abstract: At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit than the complete cell array. The signal control unit disposed on one-end side of a row of the cell arrays receives/outputs a signal from/to a global line. A read/write control unit disposed between the cell arrays controls data read/write from/to the cell arrays. The global line extends from one-end side of the row of the cell arrays to be connected to the read/write control unit. The global line is always wired on the short incomplete cell array, thereby reducing load capacitance and charge/discharge current thereof. This can reduce power consumption of a semiconductor memory, and shorten the access time thereof.Type: GrantFiled: February 27, 2006Date of Patent: April 1, 2008Assignee: Fujitsu LimitedInventor: Hideo Akiyoshi
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Patent number: 7319634Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.Type: GrantFiled: August 8, 2006Date of Patent: January 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Hwan Choo, Ho-Sung Song
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Patent number: 7272066Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.Type: GrantFiled: March 17, 2006Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventor: Dean A. Klein
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Method and apparatus for address and data line usage in a multiple context programmable logic device
Patent number: 7266020Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.Type: GrantFiled: July 19, 2005Date of Patent: September 4, 2007Assignee: Xilinx, Inc.Inventor: Stephen M. Trimberger -
Patent number: 7266038Abstract: The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a select signal (103), and a connecting line (106) for connecting each electronic circuit unit (101a-101n) to the select signal generating unit (105), each of the electronic circuit units (101a-101n) of the electronic circuit module (100) furthermore in each case having a decoder unit (107a-107n) for decoding a predetermined bit sequence (108) of the select signal (103), at least one electronic circuit unit (101a-101n) being selectively selected by means of the predetermined bit sequence (108) of the select signal (103).Type: GrantFiled: May 19, 2005Date of Patent: September 4, 2007Assignee: Infineon Technologies AGInventor: Sven Boldt
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Patent number: 7254690Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.Type: GrantFiled: May 20, 2004Date of Patent: August 7, 2007Assignee: S. Aqua Semiconductor LLCInventor: G.R. Mohan Rao
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Patent number: 7239573Abstract: The present invention is to provide a method of storing data for driving an MMC or SD under an operating system (e.g., Linux), which comprises the steps of collecting data in a plurality of discreet blocks of a high-speed buffer for each writing request made by a device driver under the OS; temporarily storing data in a plurality of continuous blocks of another buffer; and writing data from the continuous blocks of another buffer into a continuous block of the MMC or the SD in one operation in the form of multiple blocks in due time. By utilizing this method, data writing speed is significantly increased.Type: GrantFiled: April 22, 2005Date of Patent: July 3, 2007Assignee: Inventec Appliances Corp.Inventors: David Ho, Wei Yang
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Patent number: 7212448Abstract: A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.Type: GrantFiled: July 19, 2005Date of Patent: May 1, 2007Assignee: Xilinx, Inc.Inventor: Stephen M. Trimberger
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Patent number: 7193928Abstract: A signal output device includes a first selection unit operable to select a plurality of signal lines from a signal line group, a second selection unit operable to select a reference clock of signals carried by the selected signal lines, a determination unit operable to determine an output clock based on the reference clock and the number of selected signal lines, and an output control unit operable to sample the signals carried by the selected signal lines on every cycle of the reference clock and to sequentially output the sampled signals on every cycle of the output clock.Type: GrantFiled: August 1, 2005Date of Patent: March 20, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideyuki Kanzaki, Masaaki Harada
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Patent number: 7167404Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.Type: GrantFiled: May 13, 2003Date of Patent: January 23, 2007Assignee: STMicroelectronics Pvt Ltd.Inventors: Shalini Pathak, Parvesh Swami
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Patent number: 7142476Abstract: A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, including; n-stage counter which generates the row address corresponding to an address space of the normal area represented by n bits and the parity area represented by m (m<n) bits; an area discriminating circuit which generates an area discriminating signal; a first switching circuit for switching between a first connected state in which all stages of the counter are connected and a second connected state in which a n?m bits counter portion is disconnected from the counter; and an automatic reset circuit which generates a reset signal so that the count operation in the normal area is discriminated by the discriminating signal when stopping of the refresh operation in the second connected state.Type: GrantFiled: June 14, 2005Date of Patent: November 28, 2006Assignee: Elpida Memory Inc.Inventors: Takeshi Hashimoto, Masayuki Kaneda
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Patent number: 7124256Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.Type: GrantFiled: December 3, 1997Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventors: Jeffrey S. Mailloux, Kevin J. Ryan, Todd A. Merritt, Brett L. Williams
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Patent number: 7120078Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.Type: GrantFiled: September 23, 2004Date of Patent: October 10, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Kawaguchi, Shigeo Ohshima
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Patent number: 7116602Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.Type: GrantFiled: July 15, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventor: Dean A. Klein
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Patent number: 7099229Abstract: A memory block is divided into block units for which parallel data write is performed. Current supply sections capable of supplying a power supply voltage and a ground voltage are provided for block units, independently of one another. With this configuration, in each block unit, writing of data to a selected memory cell is performed by a data write current from the independent current supply section connected to the power supply voltage and the ground voltage. That is, wiring lengths of power supply lines for supplying the power supply voltage and the ground voltage can be shortened. It is therefore possible to suppress a wiring resistance of the power supply line and to supply a desired data write current.Type: GrantFiled: February 24, 2005Date of Patent: August 29, 2006Assignee: Renesas Technology Corp.Inventor: Tsukasa Ooishi
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Patent number: 7099179Abstract: Conductive memory array having page mode and burst mode write capability. The conductive memory array includes two-terminal memory plugs and driver circuits configured to write information to the memory plugs in two cycles. The array also includes associated circuitry that allows it to carry out such two-cycle writes in either page mode or burst mode.Type: GrantFiled: December 22, 2003Date of Patent: August 29, 2006Inventors: Darrell Rinerson, Christophe Chevallier
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Patent number: 7072923Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.Type: GrantFiled: February 15, 2005Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Kevin Duncan
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Patent number: 7057946Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.Type: GrantFiled: September 16, 2003Date of Patent: June 6, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Ryo Fukuda
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Patent number: 7054218Abstract: A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of pulses to the series of decoders in accordance with a difference in a stored previous address and a received current address.Type: GrantFiled: August 26, 2004Date of Patent: May 30, 2006Assignee: Intel CorporationInventor: Chen Gu
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Patent number: 7042795Abstract: A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.Type: GrantFiled: April 2, 2004Date of Patent: May 9, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Keun Lee, Jin-Sung Park
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Patent number: 7016254Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.Type: GrantFiled: August 12, 2004Date of Patent: March 21, 2006Assignee: Micron Technology, Inc.Inventors: Frankie Fariborz Roohparvar, Kevin C. Widmer
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Patent number: 6999376Abstract: A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data read from a group of columns during a burst operation. The burst columns are generated using an internal counter and an externally provided start address. The memory generates the burst column addresses by modifying the least significant column address signals only. For a burst length of two, only the least significant address bit is modified. For a burst length of four, only the two least significant address bits are modified. Finally, only the three least significant address bits are modified for a burst length of two. In one embodiment, the burst addresses rotate through the defined column group in a cyclical manner.Type: GrantFiled: April 22, 2004Date of Patent: February 14, 2006Assignee: Micron Technology, Inc.Inventor: Frankie F. Roohparvar
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Patent number: 6973006Abstract: A system and method for predecoding memory addresses by generating a sequence of predecode signals based on the memory address, providing the sequence of predecode signals as a first set of activation signals, and based on the value of the memory address, either resequencing the sequence of predecode signals and providing the resequenced predecode signals as a second set of activation signals or providing the sequence of predecode signals as the second set of activation signals.Type: GrantFiled: June 16, 2004Date of Patent: December 6, 2005Assignee: Micron Technology, Inc.Inventor: Daniel B. Penney
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Patent number: 6947302Abstract: A method and circuit for detecting multiple match conditions in a content addressable memory is disclosed. The circuit detects the multiple matches using a transistor array which is arranged as logical AND and OR gates. A current sensing detector provides multiple match detection when a current path is established through the transistor array when a multiple match exists.Type: GrantFiled: January 6, 2004Date of Patent: September 20, 2005Assignee: Micron Technology Inc.Inventor: Zvi Regev
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Patent number: 6944714Abstract: An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.Type: GrantFiled: July 30, 2002Date of Patent: September 13, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gregg B. Lesarte, John W. Bockhaus
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Patent number: 6925543Abstract: The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory, and an interface circuit which controls the first and second memories as one burst transfer memory, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.Type: GrantFiled: September 9, 2002Date of Patent: August 2, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Takahashi, Hiroyuki Koinuma
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Patent number: 6915407Abstract: A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2004Date of Patent: July 5, 2005Assignee: Intel CorporationInventors: Srinivasan T. Rajappa, Romesh B. Trivedi, Rajagopal Subramanian, Zohar Bogin, Serafin Garcia
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Patent number: 6912615Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.Type: GrantFiled: September 6, 2002Date of Patent: June 28, 2005Assignee: Koninklijke Philips Electronics N.V.Inventor: Volker Nicolai
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Patent number: 6910096Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 2, 2003Date of Patent: June 21, 2005Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6898662Abstract: An embodiment of the present invention includes a method of implementing the logical grouping of memory system sectors in a non-volatile memory system in order to increase the operational speed of the memory system, the method comprising allocating sets of contiguous logical sectors containing file data from a host system into logical groups; ensuring that a logical group includes fewer sectors than there are sector locations in a memory block in the non-volatile memory; aligning the logical groups with the clusters into which the host system organizes sectors containing file data; writing sectors within a logical group to contiguous locations within the non-volatile memory; organizing the on-volatile memory such that the corresponding sector in each logical group is written to a corresponding array within the memory; the arrangement being such that the reading then writing of a sector of a cluster to relocate it to a different location in the non-volatile memory takes place within the same array, thereby allType: GrantFiled: September 27, 2002Date of Patent: May 24, 2005Assignee: Lexar Media, Inc.Inventor: Sergey Anatolievich Gorobets
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Patent number: 6895465Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: March 31, 2004Date of Patent: May 17, 2005Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6894935Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths.Type: GrantFiled: May 19, 2003Date of Patent: May 17, 2005Assignee: Emulex Design & Manufacturing CorporationInventors: Eric Peel, Qing Xue, Sam Su, Stephen Eugene Holness
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Patent number: 6874058Abstract: A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a common data bus and to the data interface of the memory block. A switch couples the data interface of the memory block with the data bus, and a logic block including a Match flip-flop. The memory is operable in a Search phase and an Access phase. In the Search phase, a sequence of words on the common data bus is serially matched with the contents of a sequence of addresses in the memory blocks. In the Access phase, the cells matched in the Search phase are made serially available for access via common address and data buses.Type: GrantFiled: July 15, 1999Date of Patent: March 29, 2005Inventor: Douglas Philip Turvey
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Patent number: 6854040Abstract: A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.Type: GrantFiled: November 21, 2000Date of Patent: February 8, 2005Assignee: STMicroelectronics S.r.l.Inventors: Simone Bartoli, Antonino Geraci, Mauro Sali, Lorenzo Bedarida
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Patent number: 6847570Abstract: A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.Type: GrantFiled: November 21, 2002Date of Patent: January 25, 2005Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Yoshiaki Okuyama
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Patent number: 6845057Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.Type: GrantFiled: September 23, 2003Date of Patent: January 18, 2005Assignee: Micron Technology, Inc.Inventors: Kevin C. Widmer, Cliff Zitlaw, Frankie Fariborz Roohparvar
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Patent number: 6842358Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.Type: GrantFiled: August 1, 2002Date of Patent: January 11, 2005Assignee: NetLogic Microsystems, Inc.Inventor: Sandeep Khanna
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Patent number: 6826104Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.Type: GrantFiled: August 26, 2002Date of Patent: November 30, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Kawaguchi, Shigeo Ohshima
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Patent number: 6813677Abstract: There is disclosed a memory capable of storing a present value and at least one past value of a variable accessible by a first memory address. The memory comprises a memory block comprising R rows of memory cells and a row address decoder for decoding the first memory address. During a read operation, the row address decoder causes data to be retrieved from a row in which data stored to the first memory address was last written. During a write operation, the row address decoder causes data to be stored in a next-sequential row following the last-written row.Type: GrantFiled: June 2, 2000Date of Patent: November 2, 2004Assignee: STMicroelectronics, Inc.Inventor: Vidyabhusan Gupta
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Patent number: 6807121Abstract: A semiconductor memory device is disclosed that realizes the external-8K Ref/internal-4K Ref standard without lengthening the refresh cycle. Successive selection and simultaneous activation of two normal word lines that do not belong to the same mat is first carried out while preventing replacement by redundant word lines by activating a redundancy non-access signal; following which successive selection and simultaneous activation of two redundant word lines that do not belong to the same mat is carried out while preventing the activation of normal word lines by activating a redundancy access signal. Since the refreshing of normal word lines and refreshing of redundant word lines are each performed while preventing replacement of normal word lines by redundant word lines, two word lines in the same mat are not simultaneously activated even though two word lines are refreshed by means of one refresh command.Type: GrantFiled: November 13, 2002Date of Patent: October 19, 2004Assignee: Elpida Memory, Inc.Inventors: Shun Natsui, Hiroki Fujisawa
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Patent number: 6798710Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows the memory to have an efficient Flash internal structure, while logically re-mapping this architecture externally to a compatible virtual SDRAM architecture. This allows for access and operation of the improved memory device with a compatible SDRAM controller device, while Flash specific functions can be performed with an SDRAM command sequence. Internal to the memory, memory array banks are divided into four equal segments by row range and logically re-mapped by placing the segments virtually beside each other. This forms a virtual memory bank structure of equivalent rows and columns as a comparable SDRAM device. Additionally, the improved memory device may also have an extended interface that allows for direct access to the internal Flash memory architecture without logical abstraction.Type: GrantFiled: February 19, 2003Date of Patent: September 28, 2004Assignee: Micron Technology, Inc.Inventors: Frankie Fariborz Roohparvar, Kevin C. Widmer
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Patent number: 6788112Abstract: A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.Type: GrantFiled: May 12, 2003Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Rajiv Joshi, Antonio R. Pelella, John R. Rawlins, Jatinder K. Wadhwa