Abstract: A semiconductor memory is provided which has a FIFO memory in which data is read in synchronization with a read clock signal. In order to read the memory, the device has a read controller which generates a read counter clock signal in synchronization with the read clock signal and a memory read access signal, and which generates a read counter reset signal which becomes active in synchronization with the read clock signal after the reset signal becomes active. The device also has a read counter which sequentially generates first read addresses whose address values are different in synchronization with the read clock signal and is reset when the read counter reset signal is active, and an AND gate group in which second read address signals are output and first read address signals from a read counter and the reset signal are input.

Abstract: A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

Abstract: A memory device (e.g., an SRAM) is configurable to be operated in an asynchronous or a synchronous mode in accordance with a value stored in a control register thereof. In addition to asynchronous and synchronous operating modes, additional features such burst mode operations, including asynchronous burst mode operations and/or synchronous burst mode operations (e.g., linear sequential and/or interleaved burst operations); the number of pipeline stages of an output path of the SRAM; and/or the number of data hold cycles for synchronous operation of the SRAM are configurable in accordance with additional values stored in the control register.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.

Abstract: A method and system are provided which allows N programmable cells to be used to select one of 2N signals for routing to a desired destination, such as a programmable array logic (PAL), for further processing. N input selection signals are used to generate N selection signals and their corresponding complements using N programmable cells. These selection signals are then used to generate coded selection signals, which can be separated into groups of one or more. Each group of coded selection signals is then decoded, such as with K×1 tree decoders, where K is not greater than 2N. Tree decoders are typically cascaded such that the first stage or group of decoders select a portion of the 2N signals and then subsequent decoder(s) select portion(s) of the previous selected signals until the one desired signal is selected from the 2N signals. A different set of N input selection signals can be used to select a signal from the same 2N signals in order to select more than one of the 2N signals.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal.

Abstract: A method and apparatus providing parallel memory circuitry, such as for example synchronous dynamic random access memory (SDRAM) support in a computer system designed to support serial memory circuitry, such as for example Rambus dynamic random access memory (RDRAM). In one embodiment, a circuit board including a memory translator having serial memory interface logic and parallel memory interface logic is plugged into a serial memory connector on a motherboard designed to utilize serial memory circuitry. The circuit board includes parallel memory circuitry coupled to the parallel memory interface logic of the memory translator. The memory controller on the motherboard accesses the parallel memory circuitry on the circuit board through the memory translator.

Abstract: A memory device is disclosed, in which the operation of selecting the next line and relevant column addresses is unnecessary, thereby improving the data-writing/reading speed in comparison with the conventional DRAM. The memory device comprises a memory cell comprising at least two banks; and a line-address counting section for making a designated line of one of the banks active, wherein before reading or writing operation of data of the designated line is finished, the line-address counting section makes the next designated line of another bank active.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A burst-mode capable RAM chip includes a timing circuit for clocking a burst counter during a burst transfer. In response to an input indicating the beginning of the burst transfer, the timing circuit generates a first signal that loads the initial address of the burst transfer into the latches of a burst counter. Then, the timing circuit generates a second signal to increment the burst counter to the second address in the burst transfer after the load of the initial address has successfully completed but prior to the second clock cycle. Finally, the timing circuit generates subsequent signals to increment the burst counter through the remaining addresses of the burst transfer. Each of the subsequent signals is generated in response to an input from the system clock.

Abstract: A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information.