Abstract: A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The control of such spurious voltages improves device operating margins and allows the construction of larger arrays.

Abstract: In a magnetic transfer master carrier, as a substrate, one having a Young's modulus E (GPa) in the range of 85 to 250 is used. Magnetic transfer is performed under conditions in which 2??Ed3/{P(S2/S1)}?400 (where the constant ?=7.37×109) is satisfied, where d (m) is the thickness of the substrate from the bottom face of a recessed portion to the back face, S1 (m2) is the total area of the cross sections of the projected portions which are parallel to the plane of the substrate at a height of 50% of Dmax from the bottom face of the recessed portion when the height from the bottom face of the recessed portion to the top face of a projected portion is denoted by Dmax, S2 (m2) is the total area of the bottom faces of the recessed portions and the cross sections of the projected portions at the positions of the relevant bottom faces, and P (MPa) is the tight contact pressure between the master carrier and the slave medium at the time of magnetic transfer.

Abstract: A standard cell arrangement for a magneto-resistive component, comprising at least one magneto-resistive layer system, preferably in the center of the cell, in addition to at least one input and at least one output on the cell periphery. The input is provided with two input connections which can be connected to each other in order to conduct a current producing a magnetic field used to influence the magneto-resistive layer system. The output has two output connections which can be connected to the magneto-resistive layer system to pick off a signal. The input and output connections are arranged at predetermined points in relation to a rectangular basic shape of said cell (respectively mirror-symmetrical or point-symmetrical to the center of the cell).

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: This invention provides a probe based magnetic memory storage device. In a particular embodiment, magnetic memory cells are provided in an array. Each cell provides a magnetic data layer and a conductor. At least one movable probe having a tip characterized by a conductor and a soft reference layer is also provided. In addition, an intermediate layer joined to either the movable probe or each memory cell is provided. The movable probe may be placed in contact with a given memory cell, the probe and cell thereby forming a tunnel junction memory cell with the intermediate layer serving as the tunnel junction. The magnetic field provided by the probe conductor may be combined with a field provided by the cell conductor to produce a switching field to alter the orientation of the data layer. The memory cells may include a material wherein the coercivity is decreased upon an increase in temperature. The probe may also include a heat generator.

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract: A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.

Abstract: A data storage device 5 having a storage capacity of at least 8 Mbyte is surrounded by a housing including a stylus portion 23, having a tip 25 for indicating a position. The stylus permits the data storage device 5 to be used for data entry to a electronic device 19 such as a PDA which traces the position of the stylus tip. The data storage device 5 can be used in place of a conventional stylus. Thus, the user of the electronic device 19 which traces the position of a stylus is able to enjoy the advantages of a data storage device without being obliged to use an additional component.

Abstract: A method for playing multimedia files in a terminal, in which audio files are played depending on the situation when managing the stored multimedia files, thus giving the user a blind management capability for the multimedia files. The multimedia and audio files are preferably received via radio signals, in particular via digital broadcasting signals.

Abstract: An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks. In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation. In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention.

Abstract: The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment, a tag is assigned for each of several disc access commands sent by the host. Two or more queues are created, each having a queue execution mode. Which of the queues is assigned to the command depends on the command's tag.

Abstract: Method and system for saving the state of integrated circuit chips upon failure. In one aspect of the invention, a system for saving the state of an integrated circuit includes a non-volatile memory and a state-saving controller coupled to the non-volatile memory and coupled to the integrated circuit, where the state-saving controller saves the state of the integrated circuit to the non-volatile memory when a failure occurs in the integrated circuit.

Abstract: A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.

Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

Abstract: A data recording method comprising the steps of encoding user data into first error correcting codes having a first correction capability, encoding control information into second error correcting codes having a second correction capability higher than the first correction capability, generating a data stream containing the first error correcting code, the second error correcting code, and synchronization signals, wherein the second error correcting codes and the synchronization signals alternatively interleave the first error correcting codes, and recording the data stream.

Abstract: Method for fabricating a semiconductor memory element arrangement. A layer system, including a floating gate and a tunnel barrier arrangement formed on the floating gate, is formed on an electrically insulating layer. A first trench structure is formed in the layer system, and the first trench structure has first parallel trenches extending as far as the insulating layer. A second trench structure is formed in the layer system, and has second parallel trenches arranged perpendicular to the first trenches and extending as far as the insulating layer. First and second gate electrodes are formed in the first and second trench structures. The first gate electrode is adjacent to the floating gate through which first gate electrode electrical charge can be fed or can be dissipated from. The second gate electrode is adjacent to the tunnel barrier arrangement, and can control an electrical charge transmission of the tunnel barrier arrangement.

Abstract: An arrangement for protecting data saved in a memory, in which arrangement at least one memory element and at least one data processing element are combined by means of required interfaces into a data processing entity. The arrangement comprises at least one scrambler (300, 410, 600) connected to the data processing entity, which scrambler (300, 410, 600) scrambles the form in which the data to be saved in the memory element is represented and/or descrambles data saved in the memory element into plain text when data is taken from the memory element for the use of the data processing elements.

Abstract: A print order reception system for receiving an order for print services is provided with a recording medium reception port for receiving a recording medium on which image data of pictures and print order information including printing conditions for pictures to be printed are recorded in the form of electronic data in a predetermined format. A display system reads out from the recording medium received in the recording medium reception port the image data on the pictures to be printed and the print order information on the pictures to be printed and displays the image data and the print order information as an image.

Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

Abstract: An integrated circuit comprises a first circuit that receives a clock signal. A first temperature sensor senses a first temperature. Non-volatile memory that communicates with the first temperature sensor outputs calibration data as a function of the first temperature. A semiconductor oscillator that communicates with the non-volatile memory and the first circuit generates the clock signal having a frequency that is related to the calibration data.

Abstract: The invention can provide a device, such as a semiconductor device, that accesses at least one semiconductor storage medium. The semiconductor device can include a given bus master that functions as a bus master, a bus interface that controls access to semiconductor storage media based on access request from the bus master, and a clock-supply-control circuit that controls the presence of the supply of a clock to the bus master based on access state information that indicates a state of access to the semiconductor storage media. The clock-supply-control circuit can stop the supply of the clock to the bus master if the bus interface is at a BUSY state, and supply the clock to the bus master if the bus interface is not at a BUSY state. Accordingly, a power consumption of a semiconductor device that accesses at least one semiconductor storage medium can be reduced.

Abstract: According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

Abstract: A static random access memory (SRAM) unit is provided having a read control module, a write control module, and a bypass. The read control module is configured to communicate a read signal defined to read from a first address in the SRAM unit. The write control module is configured to communicate a write signal defined to write to a second address in the SRAM unit. The bypass is disposed to connect the write control module to the read control module. The bypass is further configured to prevent a simultaneous communication of the read signal and the write signal when the first address and the second address are equivalent.

Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed. Each data storage cell (10) has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit (16), writing circuits (18) and a refreshing circuit (22) apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Abstract: An object of the present invention is to provide a technique capable of assembling a device in both of a first device performing a first function with a predetermined part and a second device performing a second function without a second part, and instructing each of the first and second functions. Determining means (92) determines the presence or absence of an electronic expansion valve (91) and gives the result to a central processing unit (93). The central processing unit (93) allows a gate array (94) operate and instruct a first function including a function of performing communication between a communication network (83) and an indoor unit (92a). When there is no electronic expansion valve (EV), the determining means (92) sends a result of the determination result indicative of the absence to the central processing unit (93). The central processing unit (93) instructs a second function of making the gate array (94) inoperative.

Abstract: A semiconductor integrated circuit is provided which includes a first memory array including a plurality of first bit lines, a plurality of first word lines, and a plurality of first memory cells, the plurality of first memory cells being provided at intersections of the plurality of first bit lines and the plurality of first word lines. Each of the plurality of first bit lines has a first line and a second line connected with the first line via a first contact, in which the first line and the second line are formed of different layers from one another.

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: A method and system of fault patterns oriented defect diagnosis for memories can analyze and recognize fault patterns and failure patterns after Memory Error Catches and Analyses (MECA) are done. The existent fault patterns are compared with a pre-simulated and grouped defect dictionary that defines possible defects of different fault patterns, and the defects of memories caused from their manufacturing process or circuit layout can be detected.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: A semiconductor integrated circuit is provided, using a one-port memory cell, capable of smoothly performing a data write/read operation in accordance with an instruction from a CPU and a data read operation to display an image on a display panel. The semiconductor integrated circuit includes a memory cell having a port through which data is input to and output from a set of bit lines, a write/read circuit connected with the port via the set of bit lines, a read circuit connected with the port via the set of bit lines, a CPU-system control circuit that controls the write/read circuit so that a data write or read operation based on a write request or read request from a CPU is performed for a first period, and a display-system control circuit that controls the read circuit so that data to be supplied to a display panel is read for a second period which does not overlap the first period.

Abstract: A method of operating an electrically alterable non-volatile multi-level memory device includes settling a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract: A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

Abstract: A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based upon a random number or upon the actual count matching a multiple of the fixed number. These techniques also have application to monitoring other types of recurring events in flash memory systems or in other types of electronic systems. In another aspect of the present invention, provisions are made to maintain an accurate experience count if the memory system experiences an improper shutdown, for example in case of power loss or removal of a memory card.

Abstract: A semiconductor memory device includes word lines, bit lines, first memory cells, second memory cells, a memory cell array, a row decoder, a row driver, a column decoder, a column driver, and a sense amplifier. The first memory cell includes a magneto-resistive element which has either a first resistance or a second resistance smaller than the first resistance. The second memory cell includes a magneto-resistive element which has a resistance between the first and second resistances. The memory cell array includes the first and second memory cells disposed in intersections of the word line and bit line. The row driver supplies a first write current to the word line. The column driver supplies a second write current to the bit line. The sense amplifier amplifies data read from the first memory cell.

Abstract: A semiconductor memory device includes a nonvolatile memory section; and a volatile memory section, wherein the nonvolatile memory section includes a nonvolatile memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function for retaining charges.

Abstract: Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.

Abstract: The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one.

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract: An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.

Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.

Abstract: An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: The present invention provides a vertical current-type magneto-resistive element. The element includes an intermediate layer and a pair of magnetic layers sandwiching the intermediate layer, and at least one of a free magnetic layer and a pinned magnetic layer is a multilayer film including at least one non-magnetic layer and magnetic layers sandwiching the non-magnetic layer. The element area defined by the area of the intermediate layer through which current flows perpendicular to the film is not larger than 1000 &mgr;m2.

Abstract: The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in which initial setup data specified to determine operation conditions of the device is to be written. The device further includes a detection circuit which detects turn-on of power. The device further includes a readout circuit which reads out the initial setup data from the initial setup data region of the memory cell array upon detecting power-on by the detection circuit. The device further includes a determination circuit which determines whether the initial setup data read out by the readout circuit is effective or ineffective. The device further includes a setup circuit which sets up the device in an operative-prohibiting status when the initial setup data is determined as ineffective by the determination circuit.

Abstract: A rack mountable shelf supports a plurality of field replaceable units (FRUS) in the form of server cartridges, or blades, that each include a processor and a memory within an enclosure. The rack mountable shelf is configured to provide communal services for said server cartridges, including at least one of supplying DC operating power to the server cartridges, distributing information signals between the server cartridges and processing system management signals for the server cartridges. The communal services can also be provided by FRUs, for example with redundant power supply units and redundant combined switch/service processor units. A midplane within the shelf enables interconnection of the FRUs.

Abstract: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, i.g. a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

Abstract: A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as VCC. Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to store bits of data at first and second points (35 and 36). A first transistor (26) is coupled to the word line, the first bit line and the first point. A second transistor (27) is coupled to the word line, the second bit line and the second point. The word line voltage is changed in accordance with process parameters to allow conduction by the first and second transistors to compensate for leakage by the pair of transistors. For example, the first and second transistors may be operated in a triode mode.