Abstract: An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.

Abstract: An integrated module contains a microcontroller and a code/data memory, it being possible for an access to the memory and an external data transfer terminal to be controlled by the microcontroller during normal operation. Furthermore, the carrying out of a test sequence for the functional testing of the memory can be controlled by the microcontroller in a test operation. In a method for checking the functionality of the memory, a command sequence on the basis of which the microcontroller controls the carrying out of the test sequence is read into the module externally before the beginning of the test operation. The command sequence is executed on the microcontroller and defect data are stored in a defect data memory under the control of the microcontroller. Therefore, it is possible to carry out a self-test of the memory, but no additional BIST hardware has to be provided for this purpose.

Abstract: A non-volatile memory device is provided that can be irreversibly programmed electrically. The device includes a memory plane formed from a matrix of memory cells, with each of the memory cells including an access transistor and a capacitor. The memory cell matrix includes first groups of memory cells laid out in a first direction and second groups of memory cells laid out in a second direction. Each first group includes memory cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes memory cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together.

Abstract: An integrated memory has address inputs for applying a row address or a column address and a latency value, and an instruction decoder with a signal input. The instruction decoder uses a signal applied to the signal input to determine whether the address applied to the address inputs is the row address or the column address. If a column address is applied, an evaluation unit which is connected downstream of the instruction decoder and has evaluation inputs which are connected to the address inputs, is used to apply a latency signal corresponding to the latency value to an output of the evaluation unit.

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Abstract: Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

Abstract: A plurality of p-MOSFETs connected to a power supply line is turned on to precharge bit lines. A precharge cancel signal generated by a NOR circuit and an inverter performs precharge control to turn off the p-MOSFETs to set the bit lines in a floating state during the period of a standby mode, or turn on the p-MOSFETs to precharge the bit lines during the period of a read mode or write mode.

Abstract: A word line control circuit controls a high-level voltage value representing that a plurality of word lines are unselected in each of an access mode and non-access mode on the basis of a control signal for controlling the high-level voltage value of the word lines and a control signal output from a main decoder.

Abstract: In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the testing method carries out resetting the address of the defective region stored in the first register and the trimming value stored in the second register, and setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.

Abstract: A semiconductor memory device which can reduce the frequency of a CBR (column before row) refresh operation comprises a memory cell array having a plurality of memory cells, and a CBR refresh unit responsive to m receptions of CBR refresh commands for performing a refresh operation once for the memory cell array.

Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: The invention relates to a phase-change memory device. The device includes a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode. Additionally, other isolated lower electrodes may be formed along a symmetry line that is orthogonal to the first two isolated lower electrodes. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation structure s around a memory cell structure diode stack.

Abstract: An adapter for removable memory cards including a housing configured to receive a memory card, a connector for connection to a host system, an interface circuit interconnecting the memory card and connector and adapted to allow communication therebetween and at least one movable cover pivotably engaged with the housing and which, in a closed position, with the housing, defines a substantially enclosed cavity configured to retain the memory card. The adapter has a generally rounded and smooth outer contour and is relatively small and light weight to provide convenient carry on the person. The adapter is made of strong materials and by fully enclosing the memory card provides a physically robust removable storage device.

Abstract: Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh dock signal having a period “n” times a period of a reference dock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.

Abstract: In a flash memory, non-selected bit lines prohibited from being programmed are first charged to a predetermined level and then a pumping voltage is generated, the precharging operation to all the bit lines is completed so that a peak current due to a voltage charging concentration is suppressed or decentralized, the memory cell array is divided into two or more portions, and the bit lines are precharged; the flash memory includes a memory cell array having pages that each include memory cells and bit lines and source lines, a first circuit for charging non-selected bit lines among the bit lines to a first voltage level at a first time, a second circuit for generating a pumping voltage higher than a power supply voltage at a second time, and a third circuit for charging the bit lines to a second voltage level at a third time.

Abstract: To provide an MRAM, in which the information readout speed of the MRAM is increased up to a speed comparable to a synchronous DRAM, the MRAM includes a plurality of units each including a plurality of memory elements arranged in a matrix form, each of which includes a non-magnetic layer sandwiched between a hard layer made of a magnetic material and a soft layer made of a magnetic substance having coercive force lower than the hard layer; a plurality of bit lines arranged in parallel with each other; and a plurality of sense amplifiers connected to the respective bit lines, wherein the plurality of sense amplifiers in the same unit are activated at the same time to read out information in the unit, the units are successively changed over in synchronization with a clock pulse, and the sense amplifiers in the different units are successively activated so that information in the plurality of units is parallel outputted in synchronization with the clock pulse, and information of each of the units is continuously

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Abstract: A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

Abstract: A memory device is configured to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate line device of the memory device which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor and hence, the information that is stored.

Abstract: A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.

Abstract: An optical data storage system directs a reference beam and a data beam to a storage material having an inhomogeneous linewidth. The data beam is modulated to contain data to be stored in the storage material. The reference beam and the data beam illuminate storage cells of the storage material, causing data to be stored. The reference beam and the data beam spatially scan the cells and are frequency swept during their respective spatial scans. Data is retrieved from the cells by illuminating the storage material with the reference beam to produce a reconstructed data beam. In an embodiment, the reference beam and the data beam overlap and illuminate the storage cells simultaneously. The reconstructed data beam is detected as a heterodyne signal produced by mixing the reconstructed data beam and the reference beam in a detector.

Abstract: An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

Abstract: An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

Abstract: A magnetic random access memory or the like has a plurality of magnetic storage elements laminated on a single transistor, resulting in a reduction in the number of necessary components and a considerable enhancement in the degree of integration of the memory.

Abstract: There is disclosed a structure of a magnetic memory device for writing/reading data to/from a magnetic memory cell including a plurality of magnetic layers. The magnetic memory device includes a plurality of magnetic memory cells, each magnetic memory cell being formed to have at least three magnetic layers. The plurality of magnetic memory cells are laid out along crossings between a plurality of first lines and a plurality of second lines that cross the first lines, respectively. The magnetic memory device selectively passes a current through the first lines and the second lines, and controls directions of magnetic moments of the first, second and third magnetic layers. Thus, the magnetic memory device writes data into a specific magnetic memory cell. In this structure, each of the first lines comprises at least two word lines.

Abstract: A magnetic memory of the random access type (MRAM) contains a memory cell array formed of a multiplicity of memory cells. The memory cells are disposed in the form of a matrix at the points of intersection of word lines and sense lines and the logical data contents of which are defined by a magnetic state. The magnetic memory further contains an addressing circuit allocated to the word lines. The address circuit applies a read voltage to the word line of one or more selected memory cells, the data contents of which are to be read out. An evaluation circuit is provided that is allocated to the sense lines and receives and evaluates a sense signal corresponding to the data contents of the selected memory cell or memory cells. The evaluation circuit has a comparator circuit receiving a reference signal supplied by a reference element that is compared with the sense signal of the memory cell or memory cells to be read out.

Abstract: A non-volatile memory array includes first and second pluralities of electrically conductive traces formed on a substrate. The second plurality of electrically conductive traces overlap first plurality of traces at a plurality of intersection regions. Each of a plurality of memory cells is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one of the memory cells includes a non-linear selection element in series with a magnetic tunnel junction storage element. The non-linear selection element includes at least a first metallic electrode layer, a barrier layer and a second metallic electrode layer metal.

Abstract: A symmetric magnetic tunnel device including first and second magnetic tunnel junctions each including a pinned magnetic layer, an insulating tunnel layer and a free magnetic layer stacked in parallel juxtaposition to allow tunneling of electrons through the insulating tunnel layer between the pinned and free magnetic layers. The first and second magnetic tunnel junctions positioned in parallel juxtaposition so as to form a continuous electron path through the first and second magnetic tunnel junctions and to provide a cell signal across the first and second magnetic tunnel junctions greater than a cell signal across each of the first and second magnetic tunnel junctions individually.

Abstract: A memory circuit receives (n.times.n) data dots of an image data and stores a plurality of data dots selected from the image of data in a single address. Before the plurality of data dots are stored in the single memory, they are shifted in a transverse row direction by one bit with regard to each of the rows and are shifted in a vertical column direction by one bit with regard to each of the columns. The image data is rotated in a step-like manner by 90.degree. clockwise or anticlockwise. The image data is rotationally shifted during write/read times, and the address in which the data dots are stored is decoded in units of data dots.

Abstract: A core memory system includes an array of toroidal ferrite cores, and also includes two hundred fifty-six X lines extending through a plurality of the cores, one hundred twenty-eight Y lines extending through a plurality of the cores, and eighteen sense-inhibit lines, each extending through a respective plurality of the cores. The X lines are organized as 16 groups, the first ends of all X lines in each respective group being electrically connected together at a common junction. The common junction is connected to a first lead of a first winding of a Balun transformer. The Balun transformer includes 17 identical windings about a toroidal core. The second end of the first winding is connected to the output of an address driver/receiver circuit. The second ends of each of the 16 X lines are connected to the second leads of respective ones of the remaining 16 windings of the Balun transformer. The second leads of each of the 16 windings are connected to respective address driver/receiver circuits.

Abstract: The invention relates to a system for the reception, storage and subsequent ransmission of information. The system utilizes a main memory and an auxiliary memory. The information received by the auxiliary memory updates and corrects the information in the main memory. A timing generator controls the timing of the memory scan periods and a time normalizer is utilized to correct frequency deviations of the timing generator. A detector monitors the operation of the system.