Abstract: A data storage device includes a plurality of shunt elements having controlled current paths connected in series, and a plurality of memory cells having programmable resistance states. Each memory cell is connected across the controlled current path of a corresponding shunt element.

Abstract: A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.

Abstract: A data transmission system for transmitting data among a plurality of electronic apparatuses each having a communication function, in which power consumption of the electronic apparatuses can be reduced, and data transmission among the electronic apparatuses can be surely carried out. In a communication standby state, an information processing unit transmits a synchronous signal at given intervals of X seconds, a biological information processing unit has a reception period corresponding to a timing synchronous with the synchronous signal, and the information processing unit and the biological information processing unit are synchronized with each other. In this state, after the information processing unit transmits a data request signal, the biological information processing unit transmits data Log1 to Log3 which have respective predetermined lengths and which are obtained through a division process.

Abstract: A portable device having a Universal Unique Identifier comprises a plurality of nonvolatile memory chips and a microprocessor. The nonvolatile memory chips provide a storage space for portable device to store an embedded operation system, and each nonvolatile memory chip has a unique identifier. When the microprocessor receives a UUID reading request from the embedded operation system, a identify code reading driver is executed to read the unique identifier from a specific address of nonvolatile memory so as to reply to the embedded system based on the read unique identifier for producing a UUID.

Abstract: A semiconductor memory device includes a memory cell array in which memory cells each having six transistors 11a, 11b, 12a, 12b, 13a and 13b are arranged two-dimensionally on a semiconductor substrate. The semiconductor memory device also includes a plurality of word lines connected to each of the memory cells, and arranged on a parallel to each other along a first direction, a plurality of bit lines connected to each of the memory cells and arranged on a parallel to each other along a second direction perpendicular to the first direction, and at least two gate electrodes provided on the semiconductor substrate such that each of the gate electrodes is connected to at least one transistor of the six transistors, all of the gate electrodes 3a, 3b, 3c and 3d being arranged on the same straight line parallel to the first direction.

Abstract: A memory circuit (1) comprises at least a non-volatile random access memory (3) and a random access memory (4). The memory circuit (1) also comprises a memory controller (5) connected by a first bus (6) to the non-volatile random access memory (3) and by a second bus (10) to the random access memory (4). Thus, data can be transmitted between non-volatile random access memory (3) and random access memory (4) via the memory controller (5). The memory circuit comprises a control bus (12) connected to the memory controller (5) to control operation of the memory circuit (1). The invention also relates to a corresponding system and corresponding electronic device (2) in which the memory circuit (1) is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory (3) and a random access memory (4) are used.

Abstract: Exemplar embodiments are disclosed which allow errors in a magnetoresistive solid-state storage device, such as a magnetic random access memory (MRAM) device, to be minimized. An illustrative method includes the steps of identifying cells in the device which have a failure mode characterized by a propensity to remain in a particular orientation of magnetization, mapping the location of the identified cells, and compensating for the failure mode of a cell at a mapped location. Systems and computer readable media are also provided.

Abstract: It is an object of the present invention to provide a semiconductor memory device with a suitable redundancy circuit and an address conversion circuit, wherein external addresses are allocated to both a memory cell array which needs refresh, typically DRAM and another memory cell array which does not need refresh, typically SRAM.

Abstract: The present invention discloses a pointer generator which generates pointer values for a stack (LIFO memory). The pointer generator includes a selection input terminal and a bi-direction linear feedback shift register. The selection input terminal transmits a selection signal to the bi-direction linear feedback shift register in response to a command to read/write the stack. The fundamental structure of the bi-direction linear feedback shift register is a linear feedback shift register. After receiving the selection signal from the selection input terminal, the bi-direction linear feedback shift register performs calculation of a specific primitive characteristic polynomial, and then creates a number sequence. When the selection signal changes, the bi-direction linear feedback shift register creates another number sequence by performing calculation of another specific primitive characteristic polynomial. The two number sequences are exactly opposite to each other in order.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A semiconductor device performs read or write when read or write command with auto-precharge function is input. The semiconductor device does not carry out the auto-precharge operation until a predetermined auto-precharge delay time passes. Therefore, page mode can be performed while using read or write command with auto-precharge function.

Abstract: An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

Abstract: An improved memory transfer device includes an outer body and a transfer module disposed in the outer body. The outer body defines a insert groove on one side and encases a transfer module, one side of the insert groove corresponding to a transfer model groove insert end. The insert end extends and defines plural groove positions for accepting at least one memory card. The character of the present invention is that one of the plural groove positions accepts and uses an xD memory card.

Abstract: A disc with a temporary defect management information area and a defect management area includes a defect management area that is present in at least one of a lead-in area, a lead-out area, and an outer area, a temporary defect information area which is formed in the data area and in which temporary defect information is recorded, and a temporary defect management information area which is present in at least one of the lead-in area, and the lead-out area. Accordingly, it is possible to record user data in a recordable disc, especially, a write-once disc, while performing defect management thereon, thereby enabling efficient use of a defect management area having a limited recording capacity.

Abstract: Voltage-dropping components are bypassed during testing of the erasing of a flash memory device thereby effectively lowering the applied erase voltage to the marginal level desired (VME). These voltage-dropping components may be a plurality of diode-connected NMOS transistors. If a plurality of diode-connected NMOS transistors are used, the voltage applied to the flash macro is reduced by m*Vt, where m is the number of bypassed diode connected NMOS transistors and Vt is the threshold voltage of the NMOS transistors. In normal operation, the voltage dropping components are placed in series with the charge pump, thereby returning the voltage applied to the flash macro to the normal level (VNE).

Abstract: A semiconductor integrated circuit is provided which is capable of selecting lines of a data bus to which data is input when the number of bits of input data is different from the number of bits of the data bus with which to input data to be written into a RAM. The semiconductor integrated circuit comprises K-bit data bus lines D0 to D7 (K is an integer 2 or more) to which data is input; selection circuits SEL (0) to SEL (13) for selecting data input through an N number of the data bus lines on the high bit side or through an N number of the data bus lines on the low bit side based on a set signal when N-bit data is input into the data bus lines (N is an integer smaller than K); and a random access memory (RAM) 1 for storing data selected by the selection circuit.

Abstract: A modem utilizing a DAA having line side circuitry including a telephone network interface and system side circuitry including a host system interface. The line side circuitry and the system side circuitry are separated by a high voltage isolation barrier. In accordance with the invention, the high voltage isolation barrier and other DAA circuitry are configured such that data and control information may be communicated between the system side circuitry and the line side circuitry using a serialized digital communication protocol. In one embodiment of the invention, the line side circuitry of the modem includes detection and measurement circuitry that is programmable to measure or establish electrical characteristics (e.g., tip/ring voltage and loop current) of the telephone line interface connection. Command information for the programmable circuitry is multiplexed with data communicated across the high voltage isolation barrier.

Abstract: The magneto-resistance effect element includes: a first ferromagnetic layer serving as a magnetization fixed layer; a magnetization free layer including a second ferromagnetic layer provided on one side of the first ferromagnetic layer, a third ferromagnetic layer which is formed on an opposite side of the second ferromagnetic layer from the first ferromagnetic layer and has a film face having an area larger than that of the second ferromagnetic layer and whose magnetization direction is changeable by an external magnetic field, and an intermediate layer which is provided between the second ferromagnetic layer and the third ferromagnetic layer and which transmits a change of magnetization direction of the third ferromagnetic layer to the second ferromagnetic layer; and a tunnel barrier layer provided between the first ferromagnetic layer and the second ferromagnetic layer.

Abstract: A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.

Abstract: A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.

Abstract: A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.

Abstract: A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.

Abstract: A flash memory, and a flash memory access method and apparatus allowing memory access and error block recovery by creating a mapping table representing a physical address and status of a data block into a map block of the flash memory and referring to the mapping table. The flash memory includes a map block having a first mapping table containing a physical address allocated to each of blocks constituting a data block and status information of each of the blocks, a second mapping table containing mapping information between the physical address and a local address on each of the blocks in the first mapping table from which error blocks are excluded, and a third mapping table in which most recent mapping information is written and processed by a specified value to minimize an update operation of the second mapping table.

Abstract: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Abstract: A method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power includes receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of

Abstract: A nonvolatile semiconductor memory device improved with integration degree, in which the gate of the selection transistors is separated on each of active regions, first and second selection transistors are arranged in two stages in the direction of the global bit line, the gates for the selection transistors in each stage are disposed on every other active regions, contact holes are formed in mirror asymmetry with respect to line B-B in the connection portion for the active regions, the gate is connected through the contact hole to the wiring, the adjacent active regions are connected entirely in one selection transistor portion and connected in an H-shape for adjacent two active regions in another selection transistor portion, and the contact hole is formed in the connection -portion and connected when the global bit line, whereby the pitch for the selection transistor portion can be decreased in the direction of the global bit line.

Abstract: Described is a system and method for initializing other memory from block oriented NAND flash by central processing units (CPUs) designed for non-NAND flash. The system employs a sequential loader that avoids the use of branches, loops, and the like, to enable a portion of the sequential loader to be sequentially fetched and executed by the CPU. The fetched and executed portion of the sequential loader is configured to copy additional instructions from NAND flash into random-access memory, such that the CPU may be fully booted from the sequential loader by executing code that has been copied into the random-access memory.

Abstract: A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.

Abstract: A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

Abstract: A sidewall insulating film (11) made of a silicon oxide film is formed on the sidewall of a gate electrode (7) (word line) with an aim to reduce the capacitance to the word line serving as the major component of the bit line capacitance. Also, when openings for connecting the bit lines are formed above the spaces of the gate electrodes (7) (word lines) by the dry etching of a silicon oxide film (31) above contact holes (12), a silicon nitride film (19) to be an etching stopper is provided below the silicon oxide film (31) so as to reduce the amount of the bottom surface of the opening receded below the upper surface of a cap insulating film (9). A side-wall insulating film (11) composed of a silicon oxide film is formed on the side wall of a gate electrode (7) (word line WL) to reduce pair word line capacity components as a main component of a bit line capacity.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: A programmable conductor memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the programmable contact memory cell has an access transistor, the access transistor is switched off to decouple the cell from the bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For programmable contact memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell.

Abstract: A system and method for recording removable media (such as data CDs) that include information enabling data to be read from a proprietary standard, such as DICOM, on any predetermined computer platform without the need of specific computer hardware or software is provided. A specialist/medical facility computer receives data from a variety of sources/modalities including an image scanner, a network transporting DICOM-format data, document scanners and supporting text data therefor, and forms the data into appropriate files and directories in the DICOM format. These data files are recorded on a removable media, such as a CD, along with various applications and other information that can be executed on a computer that may not include DICOM hardware and software. To this end, the removable media can include a universal viewer application that forms associations with data stored on the media so any interested party with a PC can view the data in the same form as the original modality.

Abstract: A data holding device is provided that is capable of holding data even if the power supply is shut off and reliability in holding data is high. The data holding device 1 is provided with a data latch circuit 3 and a ferroelectric memory section 5. Ferroelectric capacitors 17 and 19 are capable of storing data in non-volatile manner. One end of the ferroelectric capacitor 17 is connected to the input node 7a of an inverter circuit 7 through a transfer gate 11. The transfer gate 11 is in the off state when data are passed. Therefore, even if input data D changes when data are passed, the change is quickly transmitted to the input node 7a, so that reliability of latching operation does not lower even if the operation is made at usual speeds.

Abstract: In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: An information processing device is provided which is capable of automatically initializing external apparatuses, when external apparatuses are connected thereto. A storage area for storing information identifying the type of external device connected to the information processing device and information identifying the characteristics of the external device is provided, and the external device connected is determined provisionally from information relating to the characteristics of an external device stored in the storage area, in cases where an external device of a type which is not present in the information processing device is detected.

Abstract: A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address.

Abstract: The present invention discloses a semiconductor memory device having a multilevel interconnection structure with no conventional limitation on the number of lines. The semiconductor memory device has a multilevel interconnection structure in which column selection lines extending in the Y direction and main word lines extending in the X direction are arranged in different layers. The layer including the column selection lines is disposed under the layer including the main word lines. In the structure, in sub-word driver areas intersecting the X direction, the main word lines are arranged in a top layer and sub-word selection lines are arranged in a layer lower than the top layer. The lower layer includes a pattern of islands. According to this interconnection structure, the number of islands can be reduced. Consequently, a plurality of power lines can be arranged between the adjacent main word lines in the sub-word driver areas.

Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits, each one allowing the selection of a respective group of matrix lines according to an address; each matrix line group includes at least one matrix line. Flag means are associated with each line group, that can be set to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

Abstract: To prevent process centralization to a master unit at the time of communications channel setting to slave units. Included are: a plurality of biometric information detection devices for detecting biometric information about attaching body such as heartbeat, and wirelessly transmitting corresponding biometric data; biometric information processing device for receiving the biometric data from each of the biometric information detection devices., and going through various types of processes such as a display process; and an information processing unit for receiving the biometric data of the biometric information detection devices from the biometric information processing device via a transmission/reception section. The biometric information detection devices determine their own communications channels, and transmit the biometric data to the biometric information processing device.

Abstract: There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

Abstract: A semiconductor integrated circuit device is provided that enables testing of an optimum test unit in a memory macro under optimum test conditions when testing the memory macro provided in the semiconductor integrated circuit device. An inner bus IB is connected to a self-test circuit, and a self-test is performed on each physical region, which is a basic region in a physical address space of a memory cell array 11. The test is performed constantly with a physical region as a basic unit and redundancy remedy of each basic unit can be performed, irrespective of an outer bus OB set in a logical address space under the control of a logical macro. At the time of the self-test, a memory macro 1 can be tested using an internal clock signal iCLK or second-latency-value information L1 that is optimum for the memory macro.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: An organic switching memory device includes a plurality of first electrode lines; an organic memory layer formed on the plurality of first electrode lines, the organic memory layer having a voltage-current hysteresis characteristic; a semiconductor diode layer stacked on the organic memory layer; and a plurality of second electrode lines formed on the semiconductor diode layer, the plurality of second electrode lines being disposed in a direction so as to intersect the plurality of first electrode lines.

Abstract: In view of the transistor off leakage increasing with device miniaturization, the invention provides a semiconductor integrated circuit capable of high-speed readout by eliminating the need for a charge replenishing transistor formerly required to hold a bit line at the “H” level, and thereby speeding up readout of stored data that causes the bit line to transition to the “L” level. To achieve this, a high-potential source line and a low-potential source line are provided. Then, the source of a memory cell is selectively connected to either the high-potential source line and the low-potential source line.

Abstract: Disclosed herein is a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.

Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on an operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particularly reliable fashion.

Abstract: In an integrated circuit having an internal supply voltage generation circuit which generates an internal supply voltage by descending an external supply voltage, there is provided an internal circuit which operates with a supplied internal supply voltage. The internal supply voltage generation circuit changes an internal supply voltage level to be generated in accordance with an operation speed of the internal circuit. Preferably the semiconductor integrated circuit includes a clock control circuit which generates an internal clock signal the frequency of which is controlled in. accordance with the operation speed of the internal circuit. When the internal clock signal is controlled to have a higher frequency, the internal supply voltage is controlled to be higher. Also, when the internal clock signal is controlled to have a lower frequency, the internal supply voltage is controlled to be lower.