Abstract: The capability to encrypt or compress the traffic over network links, thus improving the security of the link on the performance of the links, and the capability to encrypt/decrypt data stored on the storage devices without requiring specialized hosts or storage devices. In a first embodiment, traffic to be routed over a selected link needing encryption and/or compression is routed to hardware which performs the encryption and/or compression and returned for transmission over the link. A complementary unit at the second end of the link routes the received frames to complementary hardware to perform the decryption and/or decompression. The recovered frames are then routed to the target device in a normal fashion. In a variation of this first embodiment the hardware is developed using an FPGA. This allows simple selection of the desired feature or features present in the switch. The switch can be easily configured to perform encryption, compression or both, allowing great flexibility to a system administrator.

Abstract: A transmission apparatus of the present invention includes an encoder unit configured to encode data including plural layers for each of the layers, a packetizing unit configured to generate a packet based on the data encoded by the encoder unit, a determination unit configured to determine transmission intervals at which the generated packet is transmitted for each of the layers, and a transmission unit configured to transmit the generated packet at the determined transmission intervals, wherein the transmission intervals are changed for each specified packet, where the change varies with each of the plurality of layers.

Abstract: A method and apparatus for efficient provisioning of a VT/TU cross-connect includes checking a state of a control bit that specifies whether to assemble an output from multiple virtual tributary (VT1.5/VT2) or tributary unit (TU11/TU12) connections or handle the output as an synchronous transport signal (STS) or administrative unit (AU-3/AU-4) connection, and switching a predetermined number of entries together based on a state of the control bit.

Abstract: A system receives a set of datagrams and forms frames based on the datagrams, where at least one of the frames includes data associated with multiple ones of the datagrams. The system writes the frames to memory to form superframes in the memory, where each of the superframes includes multiple ones of frames. The system reads the superframes from the memory, recreates the datagrams based on the superframes, and outputs the datagrams.

Abstract: A circulating switch comprises switch modules of moderate capacities interconnected by a passive rotator. Data is sent from a one switch module to another switch module either directly, traversing the rotator once, or indirectly through at least one intermediate switch module where the rotator is traversed twice. A higher capacity extended circulating switch is constructed from higher-capacity switch modules, implemented as common memory switches and having multiple ports, interconnected through a multiplicity of rotators preferably arranged in complementary groups of rotators of opposite rotation directions. A polyphase circulating switch having a low switching delay is derived from a multi-rotator circulating switch by providing programmable rotators having adjustable relative rotator-cycle phases. A low delay high-capacity switch may also be constructed from prior-art medium-capacity rotator space switches with mutually phase-shifted rotation cycles.

Abstract: A switching system for routing information packets that can simultaneously receive a variety of packet formats. The packet formats include electronic packet transmissions, optical wave division multiplexed data (WDM) with a single frame consisting of a plurality of packets to be sent to a common output line, with each packet traveling on a separate wavelength, WDM packets where the header of an individual packet travels on a wavelength different from the remainder of the packet (i.e. the payload) and the payload either travels on a single wavelength or is subdivided into a plurality of sub-packets with each sub-packet carried on a separate wavelength, and the like. The system includes input devices, a scheduling unit, a switching unit; and variable delay line units. A deconcentrator in the packet switching system creates a minimum gap between packets.

Abstract: An apparatus, a method, and a computer program are provided for increasing the efficiency of Radio Frequency (RF) resources. Specifically, a modified Resource Release Request Message (RRRM) is utilized. The modified RRRM incorporates several additional fields that allow for the release of multiple service instances at approximately the same time. The simultaneous or near simultaneous release of multiple service instance is more efficient that the traditional RRRM for the release of a single service instance. Therefore, limited RF resources can be better preserved.

Abstract: Radio protocol for a next generation mobile communication system is disclosed including a radio link control layer for connecting to an upper layer through a service access point provided in advance and for connecting to a lower layer through a plurality of logic channels provided in advance. The radio link control layer includes at least one radio link control entity for transmission/reception of data to/from up-link or down-link according to a form of a data transmission mode.

Abstract: The invention includes an apparatus and method for switching packets through a switching fabric. The apparatus includes a plurality of input ports and output ports for receiving arriving packets and transmitting departing packets, a switching fabric for switching packets from the input ports to the output ports, and a plurality of schedulers controlling switching of packets through the switching fabric. The switching fabric includes a plurality of virtual output queues associated with a respective plurality of input-output port pairs. One of the schedulers is active during each of a plurality of timeslots. The one of the schedulers active during a current timeslot provides a packet schedule to the switching fabric for switching packets through the switching fabric during the current timeslot.

Abstract: A stackable Ethernet switch system (SESS) includes a number of stack switch elements in which loops are prevented. In one embodiment, logic is provided for monitoring control management traffic on a stacking port of a stack switch element of the SESS. Also included is logic, operable responsive to determining that there is a loss of control management traffic on a stacking port of a particular switch element of the SESS, for disabling user traffic data on that stacking port while keeping the control management traffic path open. The user data traffic on that stacking port of the particular switch element may be enabled upon detecting that the control management traffic on that stacking port has resumed.

Abstract: A transit memory assembly of a rotator-based switching node is logically partitioned into two sections, one operated as a common-memory switch fabric and the other as a time-shared space-switch fabric. The composition of data received at input ports of the switching node determines adaptive capacity division between the two sections. Based on an indication of traffic type, a controller of at least one input port selects one of the two sections. The space-switch section enables scalability to a high transport capacity while the common-memory section enables scalability to a high processing throughput. The switching node includes rotators and a bank of transit-memory devices that facilitate the incorporation of any mixture of periodic, aperiodic, contention-free exclusive-access, concurrent-access, and multicast switching.

Abstract: A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.

Abstract: Techniques for transmitting SONET/SDH traffic over an Advanced Switching compatible switch fabric. In one implementation, SONET/SDH traffic may be aggregated and encapsulated into Advanced Switching compatible packets. In one implementation, the contents of the Advanced Switching compatible packets may be configurable and directions on how to unpack the Advanced Switching compatible packets may be transmitted to end point nodes. In one implementation, SONET/SDH pointer justification generation may be divided between a source node which transmits SONET/SDH traffic to the switch fabric and an end point node which receives SONET/SDH traffic from the switch fabric.

Abstract: A system receives a set of datagrams and forms frames based on the datagrams, where at least one of the frames includes data associated with multiple ones of the datagrams. The system writes the frames to memory to form superframes in the memory, where each of the superframes includes multiple ones of frames. The system reads the superframes from the memory, recreates the datagrams based on the superframes, and outputs the datagrams.

Abstract: In one embodiment, an apparatus comprises a switch fabric, an adaptation processor to append a length field to a received packet, and a switch fabric to use information in the length field to switch variable-sized packets.

Abstract: A high capacity distributed switching system comprises electronic edge nodes connected to a balanced bufferless switch which may be electronic or optical. The balanced bufferless switch comprises a balanced connector and a switch fabric. The balanced connector comprises an array of temporally cyclic rotator units having graduated rotation shifts and each having a prime number of output ports. The switch fabric may be a mesh interconnection of switch modules. Due to the use of the balanced connector, establishing a path through the switch fabric requires at most a second-order time-slot matching process for a high proportion of connection requests with a much reduced need for a third-order time-slot matching process required in a conventional mesh structure.

Abstract: A multi-service platform system (100, 200) including a VMEbus network (102) and a switched fabric network (104) wherein the VMEbus network (102) and the switched fabric network (104) operate concurrently within the multi-service platform system (100, 200). Multi-service platform system (100, 200) can include a payload module (106) with a first switched fabric connector (210) in a P0 mechanical envelope (218) that is designed to interface with a corresponding first switched fabric connector (212) in the J0 mechanical envelope (220) on a backplane (204).

Abstract: In one embodiment, a switching system includes a backplane and multiple cards that each support multiple ASIC devices. Each ASIC device is associated with a subset of the network interfaces associated with the switching system. At least one ASIC device on a card may communicate switched data to an outgoing network interface associated with the card. Remaining ASIC devices on the card may communicate switched data to one or more other cards, using the backplane, for communication to one or more outgoing network interfaces associated with the other cards. In another embodiment, a device for switching data from a first bus to a second bus in a TDM switching system is provided. In another embodiment, a method for switching data between a plurality of network interfaces in a switching system is disclosed.

Abstract: A non-blocking time and space switch is provided, based on specific memory method functions, called replica representatives, which shows a much lower data redundancy compared with the common RAM based approach as a consequence of multiple replica representatives. This allows the monolithic implementation of high through put time space switches.

Abstract: Embodiments of the present invention generally relate to network communications. More specifically, embodiments relate to a system and method for switching data through a network. An embodiment of a switching system communicatively couples an external network to a wide area network. The system includes a plurality of edge switches communicatively coupled to the external network, a plurality of core switches communicatively coupled to the wide area network, and an interconnected matrix of switches communicatively coupled to the core switches and the edge switches and configured to forward communication traffic between the edge switches and the core switches.

Abstract: A switching module has external ports for sending and receiving data packets and mesh interfaces for internal mesh connections with other modules. A switching engine directs packets to one or other of the mesh interfaces according to the port number of a ‘destination’ or egress port on another module, as determined by a lookup. The port numbers are programmable so that the distribution of traffic through the mesh connections can be modified.

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ?X/N? groups of cells; a read-write control block receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for the group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of the group of cells are stored in the N memory modules; the MCP address being the same as the group address.

Abstract: A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Abstract: A digital cross-connect switching system that has a single-stage architecture, a scalable bandwidth, and reduced connection memory storage requirements. The scalable bandwidth digital cross-connect switching system includes a plurality of digital cross-connect building blocks. Each digital cross-connect building block includes at least one cross-connect having a plurality of input ports and a plurality of output ports, at least one connection memory communicatively coupled to the cross-connect, and at least one OR gate. Bandwidth is scaled in the digital cross-connect switching system by interconnecting predetermined numbers of the digital cross-connect building blocks. In general, the size of the digital cross-connect switching system increases as the square of the bandwidth requirement.

Abstract: Time-slot interchange (TSI) switches include a data memory having first entries therein that contain serial data received by the switch and a connection memory having second entries therein. When programmed, these second entries contain addresses of a plurality of the first entries in the data memory and switching modes that have been assigned to the plurality of the first entries. A control circuit is also provided to automatically program a block of the second entries in the connection memory with updated switching modes during an efficient burst program mode of operation. An internal bypass feature is also provided to support efficient testing/debugging of downstream devices in a communications path.

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.

Abstract: An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N×W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N×W FFs for storing output data, in which “N” corresponds to the number of input ports and the number of output ports in the N-by-N switch, and “W” corresponds to the width of each data word. Each N-by-N switch includes N×W N-to-1 selectors, and the M space/time switches include N×W M-to-1 selectors, thereby allowing an effective N×M-to-1 selection to be performed on the data words.

Abstract: An optical channel switch comprising independent optical space switches interconnects electronic data-switch modules to form a high-capacity wide-coverage network. The optical channel switch connects incoming wavelength-division-multiplexed (WDM) links each originating from a data-switch module to outgoing WDM links each terminating in a data-switch module. The optical space switches are of equal dimension, each having the same number of dual ports (input-output ports). The channels of incoming WDM links are assigned to the input ports of the space switches and the output ports of the space switches are assigned to channels of the outgoing WDM links in a manner which permits a switched path from any data-switch module to any other data-switch module even when the number of data-switch modules substantially exceeds the number of dual ports per space switch. A method of reconfiguring the channel switch in response to varying traffic demand is also disclosed.

Abstract: A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192 and STS-768. The processor supports virtual concatenation with arbitrary channel mapping at both STS-1 and STS-3c granularities. The processor also supports contiguous concatenation with STS-12c, STS-24c, STS-48c, STS-192c, etc. capacities (i.e., STS-Nc where N is a multiple of 3). In addition, the processor supports mixed concatenation where some channels are using contiguous concatenation and some other channels are using STS-3c-Xv virtual concatenation. Alternatively, the processor is able to support any virtual concatenation, any contiguous concatenation and any mixed concatenation.

Abstract: In a communications network, each network node includes a first module that handles a group of channels between its input and output ports as a route decision unit and a second module that handles a channel between its input and output ports as a route decision unit. A module state database stores module cost data of the first and second modules and a link state database stores link cost data of the links. Using the module and link state databases a route of minimum cost is determined and a connection is established between an incoming link and one of the input ports of the first and second modules and a connection is established between one of the output ports of the first and second modules and an outgoing link. The contents of the module and state databases are broadcast to the network.

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into [X/N] groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.

Abstract: A method and apparatus for synchronizing the sampling rate of digital cells in an integrated services hub. A timing signal is extracted from an asymmetric digital subscriber line. A phase-locked loop modifies the frequency of the extracted signal and generates an adjusted timing signal. The frequency of the adjusted timing signal is compared to a predetermined value. If the frequency of the adjusted timing signal falls within a predetermined range around the predetermined value, the adjusted timing signal is used to synchronize the rate of data transfer. Otherwise, a fallback timing signal is used for synchronization. When the fallback timing signal is used, the synchronization can be improved through the use of a buffering system in which the data transfer rate is adjusted based on the amount of data in a buffer block.

Abstract: Physical implementation of the switching fabric of a massive broadband switching network constructed from recursive 2-stage interconnection. The recursive 2-stage construction is realized through a hierarchical levels of implementation, including inside-chip implementation, PCB implementation, orthogonal packaging, interface-board packaging and fiber-array packaging. Smaller switches resulted from lower levels can be employed as the switching elements in the construction of a larger switch at a higher level of implementation. Such a hierarchical levels of implementation provides great flexibility and scalability in the physical realization of switching fabric and hence yields indefinitely large-scaled switches.

Abstract: Application of the technique of statistical line grouping to banyan-type networks to practically alleviate the problems of output contention, traffic fluctuation, burstiness, and so forth without incurring additional preprocessing and buffering on the input traffic by introducing alternate-routing ingredient to the unique-routing banyan-type network, but does not complicate the switching control too much through alternate routing. The concentrator composed of interconnected routing cells is employed to fill in each of the dilated nodes of the banyan-type network to give a hybrid network. An extremely simple self-routing control mechanism over the hybrid network which is the natural melting of the self-routing control inside the concentrators and the self-routing control over the banyan-type network is presented.

Abstract: A method and apparatus for scheduling, in real-time, the order in which data packets from multiple uplink channels are organized in a downlink channel of a satellite communications network. The satellite includes uplink and downlink channels for conveying data packets over channels between user terminals, ground stations and other user terminals. Queues in the satellite collect data packets from uplinks and output the data packets to the downlink using a bandwidth that is dynamically allocated. A scheduler allocates the bandwidth to at least one queue and continuously changes the amount of bandwidth allocated to each active queue while the queue is buffering data packets between the uplinks and downlink. The scheduler allocates bandwidth based upon a priority-class packet service schedule calculated based upon traffic parameters associated with each active queue.

Abstract: The present invention refers to an apparatus for time and space switching data from a first and a second input signal to a first and a second output signal, said apparatus comprising at least four switch elements, each having a first and second input port and an output port. Each one of the switch elements comprises switching means arranged to provide for time-switching of data received from said first input port to provide an output referring to said output port and selecting means for defining a signal to be outputted from said output port by selectively combining said output from said switching means and data received via said second input port, the mutual order of said data received via said second port being the same when incorporated into said signal as when received via said input port.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

Abstract: A drive unit for a machine, in particular a machine-tool, robot and the like, is described. The drive unit has several components, and each component has at least one associated component-specific function, and a uniform communication module that forms an interface with the other components. The interfaces of the various components can be connected by logical point-to-point connections or via a bus. Each component is designated with a particular type, and the communication between the components uses a type-specific communication protocol. A least one of the components is a hierarchically superior component.

Abstract: A system is disclosed for routing data cells from at least one of a plurality of source port processors to at least one destination port processor. Such a system contemplates each cell comprising a plurality of cell frame portions. In a preferred embodiment of the system of the present invention, each cell generated by the at least one source port processor is separated into its constituent frame portions. Each frame portion has associated therewith a first characteristic and a second characteristic. The cell portions are transmitted to at least one port associated with at least one crossbar chip. The at least one port is in communication with at least two of the plurality of source port processors. Each cell portion is selectively transmitted according to its first characteristic to a corresponding one of the crossbar chips. Each cell portion is selectively transmitted according to its second characteristic to a corresponding one of the ports of the corresponding one of the crossbar chips.

Abstract: A method for determining a status of a buffer for use in converting between a standard SONET and a non-standard SONET frame is presented. The method determines the buffer's almost empty or almost full status based on a length of a transport gap of the non-standard SONET frame, wherein the standard SONET frame is formatted as a STS-N, and the transport gap of the non-standard SONET frame has been rearranged to provide a longer non-data region at the beginning of the non-standard SONET frame. The method then uses the buffer's almost empty or almost full status to trigger positive or negative stuffing. The method is used for maintaining communications when using asymmetrical gapping structures.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: One embodiment of the present invention is an arrangement for establishing connectivity between the inputs and outputs of n ports in a switching system includes first and second matrices of cross points and a control circuit. The first matrix includes n×n cross points, each first matrix cross point establishing a unilateral path between two of the n ports. The second matrix includes n×n cross points, each second matrix cross point establishing a unilateral path between two of the n ports. The control circuit is associated with a first cross point of the first matrix and a complementary cross point of the second matrix, the first cross point operable to establish a unilateral path from a source port (i) to the destination port (j), the complementary cross point operable to establish a unilateral path from the destination port (j) to the source port (i).

Abstract: A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.

Abstract: An add/drop cross connection apparatus of an SDH system, comprises an aggregate unit matching device for providing matching with the aggregate units, a higher order path connection circuit for subjecting received higher order path data to cross connection by space switching, a lower order path connection circuit for subjecting received lower order path data to cross connection by space switching, and a selector for selectively delivering the data supplied from the aggregate units, higher order tributary device, and lower order tributary device, wherein the selector delivers the data to the higher order path connection circuit or lower order path connection circuit according as the data is the higher or lower order path data.

Abstract: A flexible global distributed switch adapted for wide geographical coverage with an end-to-end capacity that scales to several Petabits per second (Pb/s), while providing grade-of-service and quality-of-service control, is constructed from packet-switching edge modules and channel-switching core modules. The global distributed switch may be used to form a global Internet. The global distributed switch enables simple controls, resulting in scalability and performance advantages due to a significant reduction in the mean number of hops in a path between two edge modules. Traffic is sorted at each ingress edge module according to egress edge module. At least one packet queue is dedicated to each egress edge module. Harmonious reconfiguration of edge modules and core modules is realized by time counter co-ordination. The global distributed switch can be enlarged from an initial capacity of a few Terabits per second to a capacity of several Petabits per second, and from regional to global coverage.

Abstract: A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.