Abstract: A time/space switching component is provided with multiple functionality that includes a time switching unit, of a space switching unit of a data channel sequence correction unit and of a control unit. As a result of corresponding mode selection, the different functionalities for a switching network are obtained with a single component, resulting in a significant reduction in an overall expenditure for development and manufacture.

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A hybrid telecommunications switch includes synchronous transfer mode (STM) and asynchronous transfer mode (ATM) switch fabrics, and a controller. The controller is configured to separate incoming ATM from STM traffic and to provide access, through a connection admission control (CAC) protocol to an STM fabric for ATM traffic. In one aspect of the invention, real-time traffic, such as voice traffic, may be separated from non-real-time traffic, such as Internet email traffic. Once separated, the real time traffic may be switched through a circuit switch fabric and the non-real-time traffic may be switched through a packet switch fabric. ATM traffic, such as CBR and rt-VBR may aggregated “on-the-fly”, that is, without pre-provisioning, and switched through the hybrid switch's circuit switch fabric. ATM traffic falling into other categories is routed through a packet switch fabric.

Abstract: An apparatus and a method are provided for monitoring the switching paths of a time/space coupling network in a coupling network (SN), having an originating address generator (UAG) for generating an originating address (UA) to be switched, a target value address generator (SE) for producing an expected target value address, and a comparator apparatus (V) for acquiring and comparing a switched originating address (UA′) on a predetermined output line (AKL) of the time/space coupling network (ZRKN) with the expected target value address. In this way, the time/space coupling network can be monitored or, respectively, tested reliably and completely.

Abstract: Methods and apparatuses for laying out an integrated circuit include a first plurality of I/O ports that are positioned along the first side, a plurality of queues that are coupled to the first plurality of I/O ports, a first bus that is positioned extending from the plurality of queues toward the second side to couple a control circuit to the plurality of queues, second plurality of I/O ports that are positioned along the third side and the fourth side, and a second bus that is positioned between the control circuit and the second plurality of I/O ports to couple the control circuit to the second plurality of I/O ports, wherein the first bus and the second bus are positioned such that the respective bus lines do not cross over each other. A time and space switching apparatus and component cell permit a bit within a data line to be selected.

Abstract: An input distribution packet switch network includes a plurality of 2×2 switch elements and packet input modules for the switch network. The switch elements are arranged in multistage and connected in accordance with Shuffle type topology to constitute a N×N switch network (N=2k, k: integer number of 2 and over). The links of the leftmost and rightmost switch elements are connected to one another so that the N×N switch network can have a ring architecture. The packet input modules are distributed laterally in the switch network.

Abstract: An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N×W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N×W FFs for storing output data, in which “N” corresponds to the number of input ports and the number of output ports in the N-by-N switch, and “W” corresponds to the width of each data word. Each N-by-N switch includes N×W N-to-1 selectors, and the M space/time switches include N×W M-to-1 selectors, thereby allowing an effective N×M-to-1 selection to be performed on the data words.

Abstract: A control interface unit (1) for the realization of a simultaneous controlling of at least two logical units is provided, as well as an appertaining method, in which a control field evaluation unit (2) evaluates a transmitted control field (SF) and produces a control value (SF′). Depending on the control value (SF′), an address field conversion unit (3) converts a transmitted address field (AF) into a relevant address (ASIC-Adr), by which a data field selection unit (4) selects, dependent on the control value (SF′), a data field (DF1, DF2) that fits the address. In this way, one obtains, with the use of a common control interface, a simple and economical simultaneous controlling of at least two logical units.

Abstract: In another embodiment, an ASIC device includes a first RAM that stores a code for each of multiple first time slots. Each code is combined with corresponding data from a first bus to specify a previously stored operation. A second RAM receives the combined data and code for each first time slot and applies the specified operation for each first time slot to generate modified data for each first time slot. A third RAM stores information specifying a second time slot to correspond to each first time slot and communicates the information for each second time slot as an address. A fourth RAM stores the modified data for a previous frame and the modified data for a current frame, locates the modified data for each first time slot of the previous frame according to the address, and communicates the modified data for each time slot of the previous frame to a second bus in the corresponding second time slot while the modified data for the current frame is being stored.

Abstract: An apparatus for interconnecting a plurality of data communication network segments. The apparatus includes a switching mechanism placed between the output circuitry and the physical transmission medium. This apparatus provides high speed short latency non blocking interconnection between a plurality of network segments while providing advanced bus and management features.

Abstract: A distributed telecommunications switching subsystem (100) receives and distributes data packets passed between a plurality of switching subsystems or channel banks (102, 104, 106) and a data packet switch (110). Each channel bank (102) has a stored list of addresses. When a channel bank (102) receives a data packet, it compares the address of the data packet to its stored list of addresses, and transmits the data packet to another channel bank (104) if the address of the data packet does not correspond to any of the addresses in its stored list of addresses. The data packet is passed on until it reaches a channel bank (106) with a matching address or else it is appropriately handled by a last channel bank (106) in the chain. If the address of data packet matches an address in its stored list of addresses, the channel bank (102) passes the data packet through a subscriber interface card (120) to a customer premises equipment unit (108) corresponding to the address of the data packet.

Abstract: A method and apparatus are disclosed for spreading the component signals of a groomed input circuit through a three-stage CLOS switch network. The spreading algorithm includes sequentially evaluating each midstage switching module as to the availability of a connection between an assigned source switching module and an assigned destination switching module having sufficient spare bandwidth to accommodate one or more of the component signals. A load sharing algorithm can be used to spread the component signals among the midstage switching stages. In this way the available bandwidth of each of the midstage switching modules is evaluated for each of the component signals and each component signal is routed through the midstage switching module having the largest available bandwidth.

Abstract: A communication node to be implemented within an optical fiber communication system is described that consists of a number of individual cards inserted within a node shelf. Each card is a transponder that comprises a Short-Range (SR) transceiver, a Dense Wavelength Division Multiplexed (DWDM) transceiver, and a local switch coupled to both transceivers. The local switches of the cards are coupled together and each selectively couple the transceivers within their respective cards to the local switches of other cards so that the transceivers can be further coupled to transceivers of other cards. This allows failure and congestion protection systems to be implemented within the node while not requiring the use of a central cross-connect switch.

Abstract: A cross-connect switch (1000) is adapted for a plurality of input channels in a synchronous network. Each input channel has a pointer processor (800) including a pointer interpreter (802), an elastic store buffer (804), and a pointer generator (806). The cross-connect switch (1000) further comprises a memory-less space switch (1020) interposed between a plurality of pointer interpreters (1010) and a plurality of elastic store buffers (1030). The space switch (1020) switches selected outputs of the plurality of pointer interpreters (1010) to inputs of each elastic store buffer (1000) in response to a switching control signal.

Abstract: A set-up scheme for a cut-through connection in a network system capable of realizing a high throughput, low latency internetwork communication efficiently under an internet environment. A network node checks source/destination information of the transport layer and/or a source/destination information of the network layer of a received packet, and if the checked information satisfies a prescribed condition, determines the packet to be a trigger. Then, the network node instructs another node capable of initiating a set-up operation, which may be the network node itself, to initiate the set-up of the cut-through connection for traffic corresponding to the trigger packet.

Abstract: Permutation networks based on de Bruijn digraphs exhibit constant control complexity (wide sense non-blocking) and constant control complexity (self-routing). The cost in terms of the cross-points used for such networks is an optimal O(N log N). This non-blocking network uses fast algorithms to control in the Terabit bandwidth while providing for cost-effective switching. The network has expandable (i.e., scalable) architecture, i.e., the network can be built by interconnecting smaller non-blocking networks (e.g., small crossbars).

Abstract: This invention discloses an apparatus including an input, a series of shift registers and an output, the input arranged to receive a plurality of serial data streams, each of the data streams containing groups of data, and to take simultaneously data bits from at least some of the plurality of serial data streams and to place the data bits into the series of shift registers, such that the data bits of a given bit position in the data groups of the some of the plurality of serial data streams are placeable together in one of the shift registers, and successive bits of a part of one of the data groups are placed in a given data position across the shift registers, and the output being arranged to read out, in parallel, data of a given data position across the series of shift registers, simultaneously. A method of converting a plurality of serial data streams each carrying data groups into parts of the data groups arranged in parallel is also disclosed.

Abstract: A Synchronous Digital Hierarchy (SDH) signal cross connect architecture is realized by switching the signals as bits in the space switch. The bit signals between the space switch and the time switches are multiplexed. In this way it is possible to linearly expand the capacity of the space switch to a much larger size before its quadratic expansion begins. This invention is applicable for the cross-connection of SDH signals such as Synchronous Transport Module (STM)-1 through STM-16.

Abstract: A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: A switch module for a communication network switch comprises first and second switching units each for communicating with one or more network communication interfaces, and a switch interface connected to each of the first and second switching units and having a pair of communication ports for enabling data to be transferred on to a local communication path which is connected between the local communication ports.

Abstract: There is provided a variable rate TDM switching system comprising steps of: arranging a plurality of incoming lines and a plurality of sending lines in lattice form; providing time-division gates at cross-points of the incoming lines and the sending lines; connecting time-division temporal switches having a function of transposing the order of time slots in input TDM frames to forward stage of respective incoming lines of the time-division space switches for performing the switching between the incoming lines and the sending lines with time slot unit while holding the multiplexing, by switching these time-division gates; connecting a scheduler for concentratedly controlling the time-division gates and the time-division temporal switches to these gates and time switches; transmitting the headers of the TDM frames to the scheduler in case of inputting the header of TDM frame, and deciding the temporal switching schedule by the scheduler as to the transposition of the order of time slots in the time-division tem

Abstract: Input interfaces convert a predetermined data frame structure, such as a Sonet STS-1, into an internal format comprising a predetermined number of rows and columns, the rows being a multiple of a number evenly divisible into the bytes contained in the internal frame format. A time-space switch switches the frame format while storing a row of bytes in a data memory. Output interfaces convert the switched data to the same type of data frame format received at the input.

Abstract: A full service channel access protocol that supports the integrated transport of voice, video and data communications is provided by dividing a communication channel into a plurality of frames, dividing each of the frames into a plurality of slots, and dividing some of the plurality of slots into a plurality of mini-slots. The mini-slots are provided for use by the multiple communication sources to request the establishment of a new voice, data, or video transmission connection over the communication channel. Additionally, a second one of the plurality of slots is divided into a plurality of second mini-slots for use by the multiple communication sources to request the establishment of a new voice, data, or video transmission connection over the communication channel and for use by the multiple communication sources to augment an existing video connection over the communication channel.

Abstract: A meshed backplane has dedicated pairs of connections for high-speed serial connection in each direction between each of multiple application modules and each other application module. A management/control bus is provided for out-of-band signaling. The mesh of serial differential pairs may be used for management/control bus signals when necessary. A time division multiplexing fabric is also provided for telephony applications. A star interconnect region is provided for distribution of signals from redundant clocks.

Abstract: A traffic concentrator for combining a plurality of digital data streams into at least one higher speed digital data stream is provided. The traffic concentrator includes a plurality of inputs that are adapted to receive the plurality of digital data streams. The traffic concentrator further includes a memory that has first and second portions. The traffic concentrator also includes a control circuit that is coupled to the plurality of inputs and the memory. The control circuit generates control signals for storing data from the plurality of digital data streams in one of the first and second portions of the memory during a first time slot. The control circuit further retrieves the data from the portion of the memory during a subsequent time slot for combination and transmission as the at least one higher speed digital data stream.

Abstract: A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.

Abstract: In a switch in accordance with the principles of the present invention, switch modules that include a disassembly block, a switching core, and an assembly block are combined to implement an N×M multi-port switch that effectively connects N input ports to M output ports, provides broadcast capability, and may be non-blocking. The switch operates on data channels that all have their respective data blocks organized in the same number of bit-packs. Disassemblers within each module slice incoming data blocks into bit-packs and route the bit-packs to switching cores. A switching core within each module connects each input channel with each output channel at the bit-pack level. Assemblers within each module receive the switched bit-packs from each switching core and assemble the bit-packs into data blocks for each of the output channels.

Abstract: A serial data stream is mapped through a cross-connect via two or more parallel independent shelves. The serial data stream is split into at least two sub-streams. If the lead frame of a sub-stream contains a concatenation indicator, it is replacing by a valid payload pointer, and a split indicator is inserted into the frame. Each of the sub-streams is then mapped through the cross-connect via a respective parallel independent shelf. Finally, the sub-streams are recombined to form an output serial data stream equivalent to the original serial data stream. If the lead frame of a sub-stream contains a split indicator, a concatenation indicator is inserted into the corresponding frame of the output serial data stream to restore the concatenation of the original serial data stream. Otherwise, a payload pointer within the lead frame is replaced by a valid payload pointer in the corresponding frame of the output data stream.

Abstract: A self-configuring distributed switch is disclosed. The switch comprises a channel switch core connected by a plurality of channels to a plurality of high-capacity data switch modules. A global controller selects paths through the channel switch core and reconfigures the paths in response to dynamic changes in data traffic loads. Propagation delays between the data switch modules and the channel switch core are coordinated to keep reconfiguration guard time minimized. The advantage is a very high-capacity, load-adaptive, self-configuring switch that can be geographically distributed to serve a large geographical area.

Abstract: Multistage switching for mixed SONET VT traffic, such as VT1.5s and VT2s, is accomplished by employing an input time switch, a space switch and an output time switch. The input time switch and output time switch include VT1.5 time switches arranged to alter the time order of the input VT1.5s and VT2 time switches arranged to alter the time order to the input VT2s. The space switch includes a VT1.5 space switch arranged to order the input VT1.5s with respect to output channels in an output channel order different from the input channel order of the VT1.5s. The space switch also includes a VT2 space switch arranged to order the input VT2s with respect to output channels in an output channel order different from the input channel order of the VT2s.

Abstract: An exchange equipment using STM able to achieve an improvement of an efficiency of use and an improvement of ease of increase of terminal cards, that is, an STM type exchange, including a time switch, for performing exchange processing of time division multiplexed data, wherein a ring highway is connected via a terminal common unit to an upstream highway and a downstream highway coupled to this time switch via a highway interface unit or directly and wherein a plurality of terminal cards are connected to this ring highway. Each terminal card is provided with an add/drop unit which drops and adds the data from and to an assigned time slot on the ring highway according to control information indicating time slot assignment information determined by the control unit and adds the data and with a card control unit which controls the add/drop unit.

Abstract: A configurable bus switch is described where the bus switches are grouped into combinations as determined by logic inputs. NMOS transistors are the bus switches of choice, and programmable logic inputs select and enable groupings of these switches. Switch enable signals drive the NMOS transistor gates and turn on or off the groups according to the programmable logic inputs. Level shifting and undervoltage protection circuitry is described in preferred embodiments.

Abstract: A high-speed area-efficient cross bar switch architecture is embedded on a chip to provide connections between a plurality of ports such that multiple and concurrent point-to-point connections may be established between any devices connected to the cross bar. The cross bar is especially well adapted for distributed communication systems implemented as a system on chip. A protocol system ensures that high priority data flows through the cross bar ahead of lower priority data in the event that there are two or more devices concurrently attempting to send data to the same port. The protocol system also arbitrates between two or more devices concurrently attempting to send data to the same port, if data from such sending devices have equal priorities. In a distributed system, concurrency of transmitting and sending data can provide significant performance advantages, as semaphores and notifications are accomplished quickly. Data transfers experience minimal blocking and throughput degradation.

Abstract: A channel is described that has a backplane interface unit that selects a signal from a backplane. The backplane interface unit is coupled to a cross connect table that provides an indication where the signal may be found on the backplane. The indication is correlated to a logical label. The logical label is correlated to a frame location that the selected signal is transmitted within.

Abstract: A highway switch control system for controlling a time division multiplex highway switch of T-S-T three-stage switches in a multiprocessor typed electronic switching system, comprises a plurality of sets of first switches of time sharing switching method, second switches of highway switching method, third switches of time sharing switching method, and processors for controlling each switch, the two processors to be connected together getting information on spare time slots of the mutual switches and deciding time slots for use in the connection, thereby controlling a connection between required switches.

Abstract: A system and method for ensuring that packets are not switched out of order in a network switch capable of dynamically selecting different routing techniques. The network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. The switch may route packets using cut-through routing or early-forwarding. To ensure that packets are not switched out of order, sequence numbers may be assigned to packets as the packets are received at one of the input ports. A different sequence may be used for each output port. The output port may also track sequence numbers by storing the number corresponding to the most recently received packets from each input port. The stored value may compared with a sequence number assigned to a packet to ensure that they are within one before allowing cut-through routing.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: In a general switch, a word oriented switch and a bit oriented switch are connected such that a common input signal included data appearing in time slots is provided to both switches. The general switch further includes a device for establishing, for each one of a number of outgoing time slots, at least one of a first connection path through the word oriented switch and a second connection through the bit oriented switch, and a device for selecting, for each outgoing time slot, data from an established one of the connection path. For each outgoing time slot, only one of the connection paths is established and the selecting device selects data from the established connection path.

Abstract: A communications switching system includes a switching network and a number of access units. The switching network includes a number of multiplexing arrangements and a number of switching arrangements. In order to provide redundancy in the system, a number of multiplexing and switching arrangements are built together to form a number of combined multiplexing and switching arrangements, and a common protection switching arrangement is arranged to provide protection switching both between access units and multiplexing switching arrangements and between access units and accessing networks.

Abstract: A packet router uses high-speed superconducting circuits to process incoming data bits, read the packet header, and pass the packet header to a non-superconducting semiconductor controller. The controller determines the appropriate destination for the packet, and sends corresponding control signals to a superconducting router. The superconducting router routes each packet to its intended destination based on these control signals.

Abstract: A method and an apparatus for switching data between a set of input bitstreams and a set of output bitstreams in a circuit switched time division multiplexed network is presented. Each bitstream is divided into recurring frames and each frame is divided into time slots. Each one of the input bitstreams is received, and frames of time slot data thereof are temporarily stored in a set of memories. Each of the memories is used for storing frames of a respective bitstream of the input bitstreams. For each frame of each one of the output bitstreams, and sequentially in accordance with the order that the time slot data are to be transmitted in the respective output frame, time slot data is selectively read from frames presently temporarily stored in the set of memories, and is then transmitted into allocated time slots of the output bitstreams.

Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: To alleviate the problems associated with modifying switching software for each individual hardware components, a logical switch abstraction is provide that is separated from an underlying physical switch abstraction, the physical abstraction being dependent upon the underlying components used in the switch. The abstraction is a model of the connection paths and switching elements of the switch. By efficiently determining connections within the logical abstraction and mapping those connections in the physical abstraction, changes in underlying hardware has a minimal effect on switching software. That is, adding new hardware to the switch has minimal effect on how connections are determined through the logical abstraction. More particularly, when a hardware type is changed or added, only mapping information identifying relations between components in the logical and physical abstractions changes. Because the logical abstraction is independent of the hardware implementation, connections are more easily managed.

Abstract: A network device includes a first switch, a second switch, and a CPU. The first and second switches each include a group of ports numbered by a numbering scheme, a rate control logic for performing rate control functions related to switching data packets between the network ports, and a local communications channel for transmitting messages between the group of ports and the rate control logic. Each switch is configured to generate rate control messages based on data packet traffic to its group of ports. The CPU is coupled to the first switch and the second switch and configured to control the first switch and the second switch. A first link port of the first switch is coupled to a second link port of the second switch, and the first link port and the second link port are configured to relay the rate control messages to each other.

Abstract: A non-blocking virtual switch architecture for a data communication network. The switch includes a plurality of input ports and output ports. Each input port may be connected to each output port by a directly connected network or by a mesh network. Thus, data packets may traverse the switch simultaneously with other packets. At each output port, buffer space is dedicated for queuing packets received from each of the input ports. An arbitration scheme is utilized to forward data from the buffers to the network. Accordingly, the use of a crossbar array, and associated traffic bottlenecks, are avoided. Rather, the system advantageously provides separate buffer space at each output port for every input port.

Abstract: In an embodiment of a matrix switch circuit, a group provided with twelve 64-to-1 selectors is arranged by 64 pieces, that is, (12×64) pieces of 64-to-1 selectors are provided. Address information is input to the selector. STS-12 (one frame) in which twelve 8-bit STS-1 (unit data) are serially arrayed is input from 64 pieces of input terminals of the selector. The matrix switch circuit is further provided with a selecting circuit that selects specific unit data in the frame and 64 pieces of 12-to-1 selectors that forms unit data output from the selecting circuit in one frame and outputs it.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: In a switch structure for circuit switching, part of the space switch functionality of a time-space (TS) switch core is broken out and arranged in groups of switch adapter boards, and the TS-switch core itself is divided into a matrix of smaller and independent TS-modules that are associated with the switch adapter boards. Each group of switch adapter boards is co-operating with a predetermined row of TS-modules in the matrix for input of data to the TS-modules in that row, and with a predetermined column of TS-modules in the matrix for output of data from the TS-modules of that column. In this way, it is possible to implement the switch structure into a number of subracks with a reasonable number of interconnections between different subracks, thus obtaining a truly modular TS-switch structure.

Abstract: A SONET bus has a set of SONET mappers that transmit and receive facility signals on facility lines. Each facility line operates at a predetermined speed. Each SONET mapper generates a SONET signal by mapping the facility signals received by the SONET mapper into a predefined format for transmission. The predefined format includes timeslots associated with each received facility signal. Each SONET mapper receives a SONET signal and maps the received SONET signal into the facility signals transmitted by the SONET mapper on the facility lines. Each SONET signal includes an associated set of the facility signals. At least one counter outputs a timeslot count signal for synchronizing the timeslots of the facility signals. A set of bidirectional drivers has a mapper side and a system side. Each bidirectional driver receives the timeslot count signal.