Abstract: An improved data transmission system including multiple local area networks (LANs) coupled by a hub that further includes multiple LAN adapters coupled to the LANs, and an asynchronous transfer mode (ATM) crossbar switch coupling all LAN adapters. LAN data frames are converted into concatenated slots of an identical size and transmitted through the ATM crossbar switch. At least the requesting LAN adapter coupled to the LAN to transmit LAN data frame includes a serial communication controller (SCC) that converts a received LAN data frame into serial data. The SCC also includes a means for converting serial data to LAN data frames.

Abstract: A time:space:time switch fabric incorporating an odd integer number of spatially distributed data switches and a plurality of spatially distributed data serializers. Each data switch has a first plurality of ingress ports, an equal plurality of egress ports, and a space switch for selectably interconnecting any one of the ingress ports to any one of the egress ports. Each data serializer has an input bus for receiving signals to be routed through the switch fabric, an output bus for outputting signals routed through the switch fabric, a plurality of egress ports selectably connectible to any one of the data switch ingress ports, and an equal plurality of ingress ports selectably connectible to any one of the data switch egress ports.

Abstract: This invention describes a method for transmitting and forwarding packets over a switching network using time information. The network switches maintain a common time reference, which is obtained either from an external source (such as GPS—Global Positioning System) or is generated and distributed internally. The time intervals are arranged in simple periodicity and complex periodicity (like seconds and minutes of a clock). A data packet that arrives to an input port is switched to an output port based on its order or time position in the time interval in which it arrives at the switch. The time interval duration can be longer than the time duration required for transmitting a data packet, in which case the exact position of a data packet in its forwarding time interval is predetermined. This invention provides congestion-free data packet switching for data packets for which capacity in their corresponding forwarding links and time intervals is reserved in advance.

Abstract: A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.

Abstract: Nodes in a network transmit information among one another without the need for identifying headers. A calendar is maintained, indicating the times at which various data chunks are to be sent. When a request is made, the calendar is checked to see whether resources are free to accommodate the request. If so, the calendar is revised to reserve resources for the request.

Abstract: A switching circuit is for switching an output thereof to one of a plurality of N input clock signals which are delayed relative to one another. The switching circuit includes at least one circuit responding to a control signal to enable the transmission, on an output signal, of a new signal of the plurality of input signals. The new signal is advanced or delayed relative to a current signal of the plurality of input signals which is currently transmitted on the output signal. The at least one circuit enables the transmission of the new signal before disabling the transmission of the current signal on the output signal. This substantially prevents the production of false signals during the switching of the output signal from one of the clock signals to another.

Abstract: A method of adding a new connection (c, d) to a time:space:time switch fabric. The fabric has a set I of k input elements, a set M of m switch elements, and a set O of l output elements. Each input element contributes one input to each switch element, and each output element receives one output from each switch element. A state Sm characterizes the switch elements as a set of ordered pairs (i, j), where (i, j) &egr; Sm if and only if the jth output element is coupled to the ith input element through one of the switch elements. The range of Sm is the set of outputs of Sm such that if j &egr; range(Sm) then (i, j) &egr; Sm for some i &egr;I. The domain of Sm is the set of inputs of Sm such that if i &egr; domain(Sm) then (i, j) &egr; Sm for some j &egr; O. If a switch state Sm exists where c ∉ domain(Sm) and d ∉ range(Sm), then the new connection is added to Sm as (c, d).

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: The invention is directed to a TSSI monitoring device as well as to an appertaining method with a TSSI insertion device (1) for inserting a TSSI monitoring value (D (t0)) into a predetermined data channel (tssi) of successive time frames to be switched, and with a difference forming mechanism (2) for forming a difference (&Dgr;=(D (t0)−D(t0+k)) of data contents of the switched, predetermined data channel for immediate successive time frames. In this way, a TSSI infringement can be identified in an especially simple and cost-beneficial way in a switching network.

Abstract: A time switch for use in communications systems and method for controlling the same is provided. The control memory is controlled by using a 16 bits data bus. The lower 9 bits represent information relating to the input port and time slot, and an upper 6 bits represent information which is needed for output conversion. The use of 16 bit control provides simplicity of time switch design by removing unnecessary elements of the prior art time switch and decreases the switch set up time. In addition, the time switch of the present invention makes it possible to process gain control from inside the time switch and eliminates the need for external gain control processing.

Abstract: An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

Abstract: A packet routing technique which is stable for all networks in the presence of input blocking and output blocking. The packets injected within a network are examined and based on a historical perspective of those packets a determination is made on how to route individual packets throughout the network in a stable manner. In particular, in order to achieve complete network stability, individual switches within the network need to choose matchings, i.e., input to output port connections, that reflect the demand on each port-pair within the switches. Thus, if all packets are guaranteed to be in the network for at most a maximum number of time blocks, then a particular switch will have seen all the packets injected in the network at least that maximum number of blocks ago.

Abstract: Allowing the implementation of a strictly nonblocking cross-point space switch central stage for the switching of SDH frames or other formats. The port terminating each incoming link has a time slot interchange (TSI) unit. Each TSI unit comprises incoming and outgoing sets of TSI's. The TSI's properly arrange each byte of each row of the STM-1 frame or other formats to be in the proper position for transmission on the STM-1 links. Within the STM-1 frame structure, each row of a frame is switched in an identical manner but the column designations within a row are switched differently. In response to rearranged frames from incoming TSI's, a cross-point switch is responsive to each column of each of the rows to switch each of the bytes of that column to the appropriate outgoing TSI for rearrangement and transmission on a STM-1 link.

Abstract: A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns.

Abstract: A cross-connection apparatus for tributary unit-12 signal included in a synchronous transfer module-N signal used as a connection signal between synchronous digital hierarchy network nodes, is provided, including, an input/output and tributary unit time switching means for receiving a signal structured in the form of a frame (HEBUS) made up with an administration unit 3 signal, identifier byte and bit interleaved parity byte, performing an administration unit 3 pointer processing, virtual container 3 path overhead processing and tributary unit-12 pointer processing in order to be connected to the switching network, and thus performing a tributary unit-12 unit switching function; and a space switching means for receiving a frame (LBUS) made up with the tributary unit-12 signal, identifier byte and bit interleaved parity byte, namely, an LBUS signal, from the input/output and tributary unit time switching means, the means performing and outputting a space switching operation with the signal.

Abstract: There is shown an apparatus for switching. The apparatus for switching comprises L switching modules which switch packets, where L.gtoreq.2 and is an integer. In an embodiment, each of the L switching modules switch packets independent of any other switching module such that there is distributed switching of packets across the L switching modules. The apparatus also comprises an interconnection module which is connected to each of the L switching modules. The interconnection module that provides a passive backplane provides connectivity between the L switching modules. In an embodiment, the interconnection module provides space and time multiplexed connectivity between the L switching modules. In an other embodiment, the interconnection module is expandable without a priori knowledge of a final number of switching modules. In yet another embodiment, the interconnection module is reprogrammable in regard to connectivity between the L switching modules.