Abstract: A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital data constitutes a high bit rate uninterrupted data stream such as a video data stream in the MPEG II format. Each control interface comprises a memory circuit for storing the data to be recorded or to be read and a device for storing the data to be recorded or read in the memory circuit so as to fill the memory circuit to a predetermined level. The storing device includes a gauge for generating an information item giving the fill level of the memory.

Abstract: A method and apparatus for mapping digital data signals in an optical communication system to a data structure having a fixed frame size. A justification indicator and a negative stuff location are allocated in frame overhead to accommodate positive/negative/zero justification. A multiplexing method to establish a hierarchy of such data structures using the same technique is also described.

Abstract: A communication device and method for transmitting digital audio and video data in an isochronous communication mode, which satisfies specifications for SD-format digital interface in a transmission device using an isochronous transmission mode such as IEEE 1394 digital data transmission and reception, including: transmission time controlling means for controlling a point of time for transmitting source packets and empty packets in order to convert the transmission timing of an inner bus of a digital device to a timing predesignated in the transmission specification; a memory for storing the source packets; and a transmitter for inserting and transmitting the empty packets according to the control by said transmission time controlling means while the source packets stored in said memory are transmitted according to the control.

Abstract: A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data frames sent over wireless media. Additionally, the system and method compensate for transmitting and receiving clock variations. In one embodiment, the system uses framing of data with preamble, stuffing and signaling bits transmitted synchronously at a high data rate in the Industrial, Scientific and Medical (ISM) bands.

Abstract: A phase detecting/collating circuit collates a phase of a reception serial data input from outside through an external interface circuit, a phase of the reception data shift clock output from the clock frequency divider/corrector circuit, and a phase of a phase collating clock obtained by delaying the reception data shift clock by ¼ periodic cycle of the reception data shift clock by means of the delay circuit. By the phase collation in the phase detecting/collating circuit, if a difference in phase capable of generating a reception error in the data transmission circuit is detected, the clock shortening timing signal or the clock elongating timing signal is output. A reception clock frequency divider/corrector circuit corrects such as to shorten or elongate said reception data shift clock when a clock shortening timing signal or a clock elongating timing signal is input, respectively. With this effect, the reception operation in the data transmission circuit is executed always normally.

Abstract: A system and associated method for the synchronization and control of multiplexed payloads over a telecommunications network wherein the asynchronous timing relationships between multiplexed payloads having varied points of origin are retained subsequent to signal processing of the payloads for further transmission to a destination point. System modules 22 include a network interface section 30, a synchronization, multiplexing and control (SMC) section 50, and a processing section 110. The SMC section 50 includes network interface bus circuitry, payload segmentation and re-assembly circuitry, control and management memory and related circuitry, payload re-assembly circuitry, and processor bus interface circuitry. The processing section of module 22 provides means for data compression, echo cancellation, error correction coding, or voice and data encryption/decryption. The module 22 is dynamically configured through a software management and control interface.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Abstract: A system and associated method for the synchronization and control of multiplexed payloads over a telecommunications network wherein the asynchronous timing relationships between multiplexed payloads having varied points of origin are retained subsequent to signal processing of the payloads for further transmission to a destination point. System modules 22 include a network interface section 30, a synchronization, multiplexing and control (SMC) section 50, and a processing section 110. The SMC section 50 includes network interface bus circuitry, payload segmentation and re-assembly circuitry, control and management memory and related circuitry, payload re-assembly circuitry, and processor bus interface circuitry. The processing section of module 22 provides device for data compression, echo cancellation, error correction coding, or voice and data encryption/decryption. The module 22 is dynamically configured through a software management and control interface.

Abstract: A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit for allocating an address to each channel of the multiplex data, a RAM for holding an information group obtained by a pointer extracting process and a pointer process, and RAM controlling unit for controlling a sequence of an operation to write-in/read-out the RAM to serially conduct the pointer process on the received multiplex data, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels.

Abstract: Disclosed is an apparatus and a method for generating decoding clock signals in response to a period of write and read clock signals for decoding transmission data, which is suppressed in a form of punctured code at a code rate. The apparatus according to the present invention comprises a) a clock generator receiving a control signal and a code rate from a transmission part, for rearranging a suppressed data; b) a controller receiving a write clock signal from an external circuit and a read clock signal from the clock generator, for controlling a period of a read clock signal wherein the period of the read clock signal is correspondent to the number of data stored in the memory; c) a decoding clock generator receiving a system clock signal from an external circuit and the control clock signal from the controller, for outputting a decoding clock signal.

Abstract: A multiplexing/demultiplexing apparatus in a digital communication system with a variable frame structure and a method of controlling the same.

Abstract: A data transfer rate control method inserts a stuff packet in real time to resolve the problem present in an ATM transmission for MPEG data. The method, for controlling a data transfer rate at which coded data are transferred in an asynchronous transfer mode may include the steps of: forming the coded data for an AAL layer (ATM Adaptation Layer); calculating an insertion timing for insertion of a NULL packet; inserting the NULL packet into the coded data of the AAL layer in consonance with the insertion timing, obtained by the calculation, for the NULL packet; and transferring, in the asynchronous transfer mode, the coded data of the AAL layer into which the NULL packet is inserted.

Abstract: Mobile radio units communicate at a lower bit-rate than the conventional switching rate of a fixed network. Such calls are identified by mobile-to-mobile recognizers which identify characteristic bit streams and handle calls appropriately. An incoming mobile-to-mobile recognizer normally routes the call to a digital to A-law transcoder. An outgoing mobile-to-mobile recognizer normally routes calls to a high bit-rate digital to A-law transcoder. If a call is established between two mobile users the first--mobile-to-mobile recognizer diverts the signal received to a bit stuffer which provides three null bits for every bit received over the air interface. The null bits may be random numbers, but preferably include a recognizable pattern which can be detected by the second mobile-to-mobile recognizer. By such "bit sutffing" a 64 kbit/s signal can be generated from a 16 kbit/s signal with minimal signal processing and without the need to transcode to A-law and back.

Abstract: An apparatus for processing an order-wire signal capable of providing a high quality communication between operators through an order-wire channel for use in a synchronous add drop multiplexer(ADM) including a multiplexing unit and a de-multiplexing unit comprises: mixer for mixing two signals to generate a mixed signal, one being a voice signal of an operator at the ADM, the other being an order-wire signal received from a de-multiplexing unit in the ADM; detector for detecting a slip to generate a control signal and generating slip data; and selector for selecting one out of the mixed signal and the received order-wire signal to produce a selected signal, and transmitting the selected signal to the multiplexing unit in the ADM.

Abstract: A system for providing efficient constant bit rate distribution of variable bit-rate encoded video programs while facilitating the distribution of encoded video programs, along with Auxiliary Data of a general character, to one or more receivers. At a particular receiver, a customized augmented video program is created by inserting selected portions of the Auxiliary Data into a selected encoded video program. The encoded video portion of the augmented video program can be transmitted, decoded and displayed in real time, while the Auxiliary Data need not be transmitted in real time but can be stored locally at the receiver for real-time presentation at a later time. Real time presentation might include insertion into the video program while non real-time presentation might include insertion into non-video applications separate from the video program.

Abstract: An apparatus is used for mapping digital signal data in a data packet of a packet clock having a plurality of clock pulses wherein the data packet is composed of information data and the digital data. The ratio of the number of bits of the information data with respect to the number of bits in the data packet is M/N with M and N being positive integers and the information data includes overhead data bits and one or more data bits. The apparatus comprises a counter for counting the clock pulses to provide counted values; a gapping signal generator for generating gapping control signals based on the counted values and the ratio M/N, wherein an M number of gapping control signals are generated for every N clock pulses; and gapping device for finding overhead data bits among the information data and gapping clock pulses corresponding to the overhead data bits in response to the gapping control signals.

Abstract: A continuous synchronization adjustment algorithm is described, which continuously synchronizes frames used in digital synchronous transmissions. By letting the receiver continuously adjust the assumed frame position, rather than adjusting only once per frame as conventionally done, a significant increase in bit error rate can be achieved. When an incorrect single sync bit is detected in a frame, thereafter during the rest of the frame, the single sync bit positions that would result from an advance or delay of the frame position (e.g., due to a bit slip in the frame) are checked. The frame position is then adjusted immediately, without waiting for the beginning of the next frame. Consequently, there is a significant decrease in the number of data bits that are interpreted incorrectly or disregarded. As such, the bit error rate resulting from the present continuous algorithm is significantly improved over that resulting from prior synchronization algorithms.

Abstract: A data transmission system is used for the transmission of a large number of telephone channels between nodes in a transmission network built as a Synchronous Digital Hierarchy (SDH), where a pulse frame (e.g. STM-1) contains a large number of bytes, each of which can be used for the transmission of a telephone channel or of overhead signals for the administration of the system, and where signals from a Plesiochronous Digital Hierarchy (PDH) are introduced into the pulse frame of the Synchronous Digital Hierarchy, so that the signals from the Plesiochronous Digital Hierarchy when introduced do not occupy all the bytes in said pulse frame. At least some of the bytes of the pulse frame which are not occupied by introduction, are used for the transmission of user-specified data signals.

Abstract: An ATM cell switch has a cell multiplexer connected by a shared bus to a cell demultiplexer. In a first aspect of the invention, writing of cell data in the cell multiplexer is staggered to even out current consumption. In a second aspect, the cell multiplexer has input processors enabling it to receive cell data from input ports with different data rates, and the cell demultiplexer has output processors enabling it to send cell data to output ports with different data rates. In a third aspect, the multiplexing sequence on the shared bus is periodically altered to avoid favoring any one input port. In a fourth aspect, test pattern data are placed on the shared bus to monitor bus integrity. In a fifth aspect, the cell demultiplexer is divided into master and slave demultiplexer modules, which are coupled to different, parts of the shared bus.

Abstract: In a transmission rate converting device, a write data serial-to-parallel converter converts data input to the device to parallel data. A frame pattern generator adds dummy data to the parallel data such that each multiframe forms a multiframe pattern subjected to conversion. The parallel data with the dummy data are written to a RAM (Random Access Memory) included in a FIFO (First-In First-Out) memory via a write port and then read thereoutof. A read data parallel-to-serial converter converts the parallel data read out of the RAM to serial data. A clock comparison and control controls a write clock generator and a read clock generator such that the number of frames stored in the RAM remains in a predetermined range.

Abstract: A system for controlling signal transfer between a plurality of devices, for controlling the transfer of signals between a main device having processors packaged therein and a subsidiary device having units packaged therein, includes a multiplexer section on the main device side for multiplexing signals from a control system processor and a monitor system processor of the main device; a demultiplexer section on a subsidiary side for demultiplexing the multiplex signal from the multiplexer section on the main device side and distributing it to the units of the subsidiary device; a multiplexer section on the subsidiary device side for multiplexing the signals from the units of the subsidiary device; and a demultiplexer section on the main device side for demultiplexing the multiplex signal from the multiplexer section on the subsidiary device side and distributing it to the control system processor and the monitor system processor.

Abstract: The present invention provides a method for achieving alignment of the header fields of a specific layer, such as the transport layer header fields, at a receiving host. The receiving host determines a number of padding bytes that need to be added to the transport layer header for the fields to be properly aligned in the memory of the receiving host. This number is determined dynamically for each connection because different connections require different numbers of padding bytes. The number of padding bytes for a connection is determined by the receiving host from the first packet received for a particular connection. Specifically, the receiving host examines this first packet and determines the position of the first byte of the transport layer protocol header, and therefore, the number of padding bytes required to achieve 32-bit (or 64 bit) alignment. The receiving host communicates the number of padding bytes to the transmitting host.

Abstract: A method for desynchronization in a receiver in a digital transmission system, where justification is performed as required by introducing or removing a single bit in the transmitted bit flow on the transmission side when placing telephone calls in the transmission system, and where, on the transmission side, adjustments are moreover made in the transmission system as required by introducing or removing groups of bits in the transmitted bit flow, smooths the effect of the introduced and removed bits in the receiver by the desynchronization. The effect of the introduced and removed bits in the receiver is smoothed in two stages, so that in one stage just the effect originating from said groups of bits is smoothed, and in the other stage just the effect originating from said individual bits is smoothed.

Abstract: A clock recovery circuit is coupled to an elastic storage circuit such as a FIFO circuit. More specifically, a first input of the elastic storage circuit is electrically connected to an output of the clock recovery circuit. A second input for accepts a data signal representing an input data stream from a communications medium. A third input accepts a local clock signal. The resultant circuit may be used in receiver's for communications systems to help alleviate the problems of frequency mismatch and jitter.

Abstract: A data receiving apparatus receives data into which a stuff pulse for frequency synchronization is inserted. The data receiving apparatus is provided with a frame alignment information detecting unit for detecting frame alignment information to establish a frame alignment from the received data, a stuff pulse insertion position detecting circuit for detecting the insertion position of the stuff pulse which has been inserted into the received data, and a frame pattern rearranging circuit for rearranging the frame pattern of the received data so that the insertion position of the stuff pulse is fixed at a predetermined position, on the basis of the detection output of the frame alignment information detecting unit and the detection output of the stuff pulse insertion position detecting circuit.

Abstract: For this system and for this equipment there has been provided a phase alignment device (30) which has an access for input data (50) applied to an access (51) at a rate of a first clock signal, and an access (70) for producing at the rate of a second clock signal applied to an access (71) a justifiable data stream, in which stream bits can be inserted or deleted. The data are written and read in and from a common memory (60) by means of a write counter (55) and a read counter (80), respectively. A comparing element (90) measures the difference of the contents of said counters (55) and (80). With each variation of this difference, intermediate steps are added with the elements (95), (97) and (98), so that the means (92) controlling the justification can be formed by a sigma-delta modulator which has a 0.5 threshold.

Abstract: Multiple speech bit-stream frame buffers are used between the controller and the speech decoder. Whenever excessive or missing speech packages are detected, the speech decoder switches to a special corrective mode. If there is too much, the buffered frames are played out fast; if there is too little the buffered frames are played out slowly. For the fast play, some speech information has to be discarded, while for the slow play some speech-like information has to be synthesized. The speech may be handled in sub-frame units, which may be 52 samples at a time. Low energy, silent or unvoiced sub-frames, which also indicate non-periodicity, are detected and manipulated. Moreover, the decoded signal is manipulated at the excitation phase, before the final LPC synthesis filter, resulting in a transparent perceptual effect on the manipulated speech quality. Additionally, the buffers are enlarged such that the problem caused by controller asynchronicity is eliminated.

Abstract: A synchronization method for synchronizing a plurality of base stations in a TDMA communication system is disclosed. The synchronization topology may be via dedicated hardwire, via any DSL from the PSTN, or via an ad-hoc RF synchronization technique. Slots containing data are arranged in frames and these frames are transmitted to the base stations, and received from the base stations, by wireless telephone handsets. Each of the slots in a frame have a guard field comprising a plurality of guard bits. The base stations derive frame sync pulses via the received Unique Word correlation detect. These derived frame sync pulses are ultimately synchronized with frame sync signals received from the master base station.

Abstract: An apparatus and method, applicable to variable bit rate video and constant bit rate video, is disclosed for replacing "stuffing bytes" with private data. The invention takes advantage of the otherwise wasted resources dedicated to "stuffing" in a data stream in order to insert private data. This is accomplished by inserting useful private data in a Transport Stream instead of the stuffing bits. That is, effectively, a re-multiplexing operation occurs where, based on the existence of certain conditions in a Transport Packet (e.g., stuffing bytes exist), the information necessary to replace stuffing bytes with private data yet still comply with established standards is accomplished. This data generally is referred to as privatestuff data in order to distinguish it from typical private data which may otherwise be encoded into a Transport Stream. The stuffing bytes removed from the Transport Packet may come from an adaptation field in the Transport Header or directly from the Transport Payload or both.

Abstract: On transferring a tributary unit (TU) from an input frame of an input signal (10) onto an output frame of an output signal (11), a recognition circuit (14) recognizes the TU of the input frame and produces not only a location signal representative of a location of the TU in the input frame But also a sort signal representative of a sort of the TU in the input frame. A threshold determining circuit (32) determines an optimum stuff threshold value (33) in response to the sort signal to produce the optimum stuff threshold value. A write controller (15) controls writing of the TU of the input frame in a memory (12) in response to the location signal by supplying a write address signal (17) to the memory. A read controller (18) controls reading of the TU out of the memory in response to a stuff request signal (19) by supplying a read address signal (23) to the memory.

Abstract: A stuff bit synchronization system synchronizes high-speed signals utilizing low-speed components. Since the respective components operate at low speeds, the power consumption and calorific value are reduced in the stuffed synchronous system. The stuff bit synchronization system includes a transmitter for transmitting a digital signal. The transmitter includes a buffer for temporarily holding the digital signal to be transmitted and a reading controller that reads contents of the buffer in parallel and provides a stuffing bit. The stuff bit synchronization system also includes a receiver for receiving the digital signal and for removing the stuffing bit from the digital signal.

Abstract: A method and system is provided for minimizing resynchronization delays in a digital microwave radio system by, immediately upon detecting a signal degradation such as a loss of signal or an out-of-specification signal at any one of a series of digital microwave radio transmitters, setting the transmitter's elastic buffer to an average condition and thereby minimizing frequency offsets at all downstream transmitters and receivers during the degradation period.

Abstract: An SDH transmission system including a container selection unit for selectively extracting a specific virtual container VC-m of a particular hierarchy from among the uppermost layer virtual containers VC-4 obtained from a demapping circuit that is a part of the SDH transmission system, and a path overhead processing unit for processing the path overhead of the specific virtual container VC-m obtained from the container selection means. Whereby, it is possible to extract and check the path overhead of the through path and to facilitate maintenance and inspection.

Abstract: A multipoint video conference system (8) is provided that has video rate control and allows communication of audio, video and data information between end-point units (16). The multipoint video conference system comprises a multipoint control unit (10, 20) having a plurality of interface units (12, 22) located therein. Each interface unit (12, 22) is operable to communicate with other interface units (12, 22) via a backplane (14, 24) of the multipoint control unit (10, 20). A plurality of end-point units (16) are each coupled to an associated interface unit (12, 22). Each end-point unit (16) is operable to communicate and process real data information and operable to receive and resend fill data information. The multipoint control unit (10, 20) is operable, with respect to each participating end-point unit (16) in a data channel, to allow communication of real data information and, with respect to each non-participating end-point unit (16), to allow communication of an equal amount of fill data information.