Synchronizing Patents (Class 370/503)
  • Patent number: 11973581
    Abstract: The time synchronization of a network is protected against unauthorized changes to the grandmaster clock of a base time domain by monitoring the physical communication interfaces of a network device for arrival of messages relating to time synchronization. If the messages relating to time synchronization apply to the initially set-up and synchronized base time domain, a check is performed to determine whether the messages relating to time synchronization announce a new grandmaster clock having better clock parameters than those of the present grandmaster clock. If so, a virtual base time domain is started by the network device. If the verification reveals that the proposed new grandmaster clock is trustworthy or valid, the network device discontinues the virtual time domain, updates its stored information concerning the grandmaster clock and, from this time onward, sends messages relating to time synchronization that are based on the new clock parameters to the network.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: April 30, 2024
    Assignee: Continental Automotive Technologies GmbH
    Inventors: Helge Zinner, Julian Brand
  • Patent number: 11973630
    Abstract: An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Spear, Daniel Mark Dreps, Erik English, Jieming Qi, Michael Sperling
  • Patent number: 11966271
    Abstract: An Ethernet communication device includes a data interface and circuitry. The data interface is configured for communicating with a neighbor device. The circuitry is configured to exchange Ethernet data frames with the neighbor device over the data interface, wherein successive data frames are separated in time by an Inter-Packet Gap (IPG) having at least a predefined minimal duration, and to further exchange with the neighbor device, over the data interface, during the IPG between Ethernet frames exchanged on the data interface, a wake-up/sleep command that instructs switching between an active mode and a sleep mode.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 23, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Dance Wu, Christopher Mash, Daryl J. Hoot, Hong Yu Chou
  • Patent number: 11968636
    Abstract: A communication method implemented by a base station having at least one cell and forming part of a mobile access network including neighbouring cells of the cell. The method includes broadcasting blocks referred to as SSB blocks at a first periodicity value for synchronising a terminal and for allowing said terminal to receive SIBs of which at least one of said SIBs includes an identifier of at least one neighbouring cell, a second periodicity value of SSB blocks broadcast by said neighbouring cell and a frequency position of an SSB block of said neighbouring cell.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 23, 2024
    Assignee: ORANGE
    Inventors: Raphaël Visoz, Benoït Graves
  • Patent number: 11966676
    Abstract: A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: April 23, 2024
    Assignee: Fermi Research Alliance, LLC
    Inventors: Sandeep Miryala, James Richard Hoff, Grzegorz W. Deptuch
  • Patent number: 11968635
    Abstract: Methods, systems, and devices for wireless communications are described. A base station may determine a terrestrial characteristic of a cell associated with the base station. A UE may perform a synchronization procedure with the cell and may receive, as part of the synchronization procedure, broadcast signaling associated with the cell. The broadcast signaling may identify the terrestrial characteristic of the cell. The base station may initiate communications with the UE based on the broadcast signaling including the indication of the terrestrial characteristic of the cell.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: April 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Ayan Sengupta, Alberto Rico Alvarino, Xiao Feng Wang, Liangping Ma, Bharat Shrestha
  • Patent number: 11956092
    Abstract: A communication system includes a master device, a connector, a superordinate trunk cable connecting the master device and the connector, a superordinate slave device connected to the connector, a subordinate slave device, and a subordinate trunk cable connecting the connector and the subordinate slave device. The connector includes a superordinate power line via which power is supplied from the master device, a power branching unit to divide the superordinate power line into a first power line connected to the superordinate slave device and a second power line connected to the subordinate slave device, a superordinate signal line via which communication data between the master device and the superordinate slave device is configured to be transmitted, and a subordinate signal line via which communication data between the superordinate slave device and the subordinate slave device is configured to be transmitted.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: April 9, 2024
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Hidetsugu Koga, Kunihiko Ogawa, Isamu Matsumura, Junya Hisamatsu, Yasuhiro Matsutani
  • Patent number: 11953938
    Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Peter Hochschild, Alexander Lloyd, Wilson Cheng-Yi Hsieh, Robert Edman Felderman, Michael James Boyer Epstein
  • Patent number: 11949767
    Abstract: A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 2, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsumasa Abe
  • Patent number: 11943750
    Abstract: The present invention relates to a wireless communication method and a wireless communication terminal for wideband link setup, and more particularly, a wireless communication method and a wireless communication terminal for increasing data communication efficiency by extending a data transmission bandwidth of a terminal. To this end, provided are a wireless communication method of a terminal, including: obtaining first primary channel information of a basic service set (BSS) with which the terminal is associated; performing clear channel assessment (CCA) for one or more secondary channels of the BSS; and setting a second primary channel among one or more secondary channels determined to be idle based on a result of the CCA, and a wireless communication terminal using the same.
    Type: Grant
    Filed: December 31, 2022
    Date of Patent: March 26, 2024
    Assignees: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC., SK TELECOM CO., LTD.
    Inventors: Jinsoo Ahn, Yongho Kim, Jinsam Kwak, Juhyung Son
  • Patent number: 11943727
    Abstract: A synchronization signal block sending and receiving method and apparatus are described. The method includes a first terminal determining, based on a correspondence between information about locations of M antenna panels and P synchronization signal blocks of the first terminal and information about locations of N antenna panels, a synchronization signal block corresponding to each of the N antenna panels, where the information about the locations of the M antenna panels is used to indicate the locations of the M antenna panels on the first terminal, the N antenna panels are included in the M antenna panels, N is less than or equal to M, M, N and P are positive integers, and P is an integer multiple of M. Then, the first terminal separately sends, by using each of the N antenna panels, the synchronization signal block corresponding to each of the N antenna panels. This application is applicable to a V2V scenario.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 26, 2024
    Assignee: HUAWEI TECHNOLOGIES CO. LTD.
    Inventor: Pu Yuan
  • Patent number: 11937196
    Abstract: Methods, systems, and devices for wireless communications are described. In an example, a method includes a first node receiving a precision time protocol (PTP) message, identifying one or more timing domains to be supported by the first node based at least in part on the PTP message, and sending, to a second node of the wireless communication network, an indicator of the one or more timing domains to be supported by the first node. Another example at a node includes receiving, from additional nodes of the wireless communication network, indicators of one or more timing domains supported by the additional nodes, receiving a PTP message associated with a timing domain, and sending the PTP message to a subset of the additional nodes based at least in a part on the indicators of one or more timing domains supported by the additional nodes.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: March 19, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Vinay Joseph, Rajat Prakash, Peerapol Tinnakornsrisuphap, Fatih Ulupinar
  • Patent number: 11930071
    Abstract: Provided is a network adapter for unidirectional transmission of a user data stream to a bidirectional network interface, the network adapter including: a first connection unit which is physically connected to a bidirectional network interface of a first device; a second connection unit which is physically connected to a bidirectional network interface of a second device; and a terminating unit which has at least one bit transmission module and which is designed to establish a bidirectional data link to the network interface of the first device, to receive the user data stream from the first device exclusively in a unidirectional fashion via the data link, and not to send a user data stream to the first device.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 12, 2024
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Rainer Falk, Stefan Seltzsam, Hermann Seuschek, Martin Wimmer
  • Patent number: 11907004
    Abstract: A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 20, 2024
    Assignee: ETOPUS TECHNOLOGY INC.
    Inventors: Tze Yin Cheung, Paul K. Lai, Danfeng Xu
  • Patent number: 11899061
    Abstract: A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 13, 2024
    Assignee: Apple Inc.
    Inventors: Fabien S. Faure, Si Chen, Mansour Keramat, Arnaud J. Forestier
  • Patent number: 11902919
    Abstract: Embodiments of this application provide a synchronization signal transmission method, a network device, and a terminal device. The method includes: determining, by a network device, time domain positions for sending m synchronization signal blocks, where the time domain positions are {s1, s2, . . . , sm}+n×T, s1 represents a start symbol index of the first synchronization signal block in a time unit, s2 represents a start symbol index of the second synchronization signal block in the time unit, sm represents a start symbol index of an mth synchronization signal block in the time unit, the time unit includes T symbols; and sending, by the network device, the synchronization signal blocks to a terminal device in the time domain positions of the synchronization signal blocks. The technical solutions provided in this application have relatively high flexibility, and can meet, to some extent, a synchronization signal block sending requirement for a high-frequency technology.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: February 13, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kuandong Gao, Huang Huang, Mao Yan, Hua Shao
  • Patent number: 11892958
    Abstract: The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 11876746
    Abstract: This disclosure provides a data transmission method and a communications device. The data transmission method includes: generating a plurality of RRC segments by using an RRC segmentation function of an RRC layer entity of the sender communications device or an RRC segmentation function of a new protocol layer entity, where each of the plurality of RRC segments carries partial data content of an RRC message generated by the sender communications device; and sending the plurality of RRC segments to a receiver communications device.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 16, 2024
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Jing Liang, Yue Ma, Yumin Wu
  • Patent number: 11870554
    Abstract: A network node device of an area network includes physical layer (PHY) circuitry configured to transmit and receive frames of data via a communication link of the communication network; medium access layer (MAC) circuitry; a receive interface between the PHY circuitry and the MAC circuitry, and timestamp circuitry. The receive interface includes a receive clock signal and a DLL. The timestamp circuitry is configured to produce multiple sample signals derived from the receive clock signal using the DLL and a local clock signal of the network node, and produce a timestamp offset using the multiple sample signals. The timestamp offset is representative of an instantaneous phase offset between a local clock of the network node and a local clock of a neighbor node of the network node.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 9, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Andrew David Alsup
  • Patent number: 11863656
    Abstract: A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: January 2, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Ian R. Knowles
  • Patent number: 11864031
    Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), a signal to configure the UE to perform a Random Access Channel-less (RACH-less) handover to a second cell may be received in a first cell. The signal may comprise an uplink (UL) grant to be used in the second cell. The UL grant may be associated with a downlink (DL) signal. Whether to use the UL grant in the second cell may be determined based upon whether the DL signal is qualified.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 2, 2024
    Assignee: ASUSTek Computer Inc.
    Inventors: Hsin-Hsi Tsai, Yu-Hsuan Guo
  • Patent number: 11855760
    Abstract: The accuracy of an offset value is improved by correcting an error in time synchronization caused by link asymmetry. PTP packets are exchanged between a master node 3 and a slave node 4 vis a first transmission device 1 connected to the master node 3 and a second transmission device 2 corresponding to the first transmission device 1 and connected to the slave node 4.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: December 26, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masahiro Nakagawa, Kaoru Arai, Hiroki Sakuma, Shunichi Tsuboi
  • Patent number: 11855758
    Abstract: Apparatuses, methods, and systems for dynamically estimating a propagation time between a first node and a second node of a wireless network are disclosed. One method includes receiving, by the second node, from the first node a packet containing a first timestamp representing the transmit time of the packet, receiving, by the second node, from a local time source, a second timestamp corresponding with a time of reception of the first timestamp received from the first node, calculating a time difference between the first timestamp and the second timestamp, storing the time difference between the first timestamp and the second timestamp, calculating a predictive model for predicting the propagation time based the time difference between the first timestamp and the second timestamp, and estimating the propagation time between the first node and the second node at a time by querying the predictive model with the time.
    Type: Grant
    Filed: April 2, 2023
    Date of Patent: December 26, 2023
    Assignee: Skylo Technologies, Inc
    Inventors: Meghna Agrawal, Andrew Nuttall
  • Patent number: 11847079
    Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: December 19, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Eyuel Zewdu Teferi
  • Patent number: 11838202
    Abstract: A master device according to this disclosure which communicates with a plurality of slave devices to share cyclic data includes: a configuration information acquiring unit to acquire a phase difference of each of the slave devices determined based on a number of other slave devices to be relayed when the each slave device communicates with the master device; and a transmission timing determining unit to calculate a hop count from a number of other slave devices to be relayed when the each slave device communicates with the master device or another slave device based on the phase difference acquired by the configuration information acquiring unit and to determine a transmission timing for each slave device to transmit the cyclic data in such a way that communications with a same hop count are performed at a same timing by the plurality of slave devices.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 5, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yuina Nakashio
  • Patent number: 11831402
    Abstract: A slave node (300) is slave equipment that operates in accordance with a control frame transmitted from a master node (200). The slave node calculates a control frame statistic that is a statistic of one or more control frames transmitted from the master equipment and estimates a master environment value based on the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock based on the estimated master environment value and estimates a frequency deviation of a slave clock based on the measured slave environment value. The slave node modifies a clock value of the slave clock based on a difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: November 28, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akio Idehara, Hirotaka Motai, Yurika Terada, Bampei Kaji, Toshiyuki Otani
  • Patent number: 11832070
    Abstract: A microphone device includes a number N of at least two serially coupled microphones forming a microphone chain. The microphones are configured to transmit data to a controller via the microphone chain. The microphone chain is configured to output time-multiplexed data transmitted by the microphones.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: November 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Victor Popescu-Stroe, Matthias Boehm
  • Patent number: 11824696
    Abstract: Messages are transmitted in closely-spaced subcarriers in 5G and 6G, configured so that each subcarrier signal is orthogonal to the adjacent subcarrier signals. However, many effects can penetrate that orthogonality—distortion, interference, frequency variations, amplitude variations, crosstalk, etc.—collectively termed energy spill-over. To combat this problem, a receiver can determine the total energy spill-over into adjacent subcarriers by measuring a residual signal in a subcarrier with no transmission, adjacent to another subcarrier with a known transmission. The receiver can measure the amplitude, phase, temporal or spectral properties, and so forth of the residual signal. The receiver can then correct the message during signal processing, by calculating a function of the residual signal and subtracting it from each digitized subcarrier signal of a message.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: November 21, 2023
    Inventors: David E. Newman, R. Kemp Massengill
  • Patent number: 11816051
    Abstract: In some implementations, a device may receive, via a universal serial bus (USB) interface, configuration information and a supply of power from a network device. The device may receive, via an antenna that is external to the device, a first signal indicating timing information. The device may generate, based on the first signal, a second signal and a third signal, wherein the second signal comprises a one pulse per second signal and the third signal comprises a ten-megahertz signal. The device may provide, to the network device, the second signal and the third signal. The device may receive, via an input port, a clock signal to provide an extended holdover functionality to the network device.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: November 14, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: John B. Kenney, Kamatchi S. Gopalakrishnan, Jack W. Kohn, Sushma B. Bavache, Amit Verma, Rafik P.
  • Patent number: 11811665
    Abstract: A network device comprising a set of queues and a time-aware shaper which comprises a set of transmission gates and gate control instructions. The gate control list comprises a set of individual gate control lists, each individual gate control list configured to control a respective gate and which comprises a sequence of entries, each entry comprising a duration of time.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 7, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Thorsten Hoffleit
  • Patent number: 11811505
    Abstract: The Digital Time Processing using Rational Number Filters (DTP RNF) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks, synchronous to referencing frames communicated with PTP messages or compatible with them data receiver clocks, for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages or by other means, wherein such distribution of the master time includes filtering out phase noise of the timing referencing signals with the Rational Number Filters in order to produce accurate and stable timing implementing signals such as the slave clock, local slave time and local master time.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: November 7, 2023
    Inventor: John W. Bogdan
  • Patent number: 11804920
    Abstract: A signal transfer management apparatus manages operations of a plurality of signal transfer devices. The signal transfer management apparatus includes a gate calculation unit configured to calculate a gate start time of each of uplink time gates and a gate start time of each of downlink time gates of a plurality of signal transfer devices and open each of the time gates, a comparison unit configured to compare uplink time synchronization messages from the plurality of slave devices to a master device and detect a conflict between the uplink time synchronization messages, and an offset unit configured to, when the comparison unit detects a conflict, adjusts the gate start time of each of the uplink time gates and the gate start time of each of the downlink time gates of the signal transfer devices and set the adjusted gate start times in the signal transfer devices.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: October 31, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Keita Takahashi, Naotaka Shibata, Jun Terada
  • Patent number: 11805026
    Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 31, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
  • Patent number: 11799599
    Abstract: A receiver includes an interface and a processor. The interface is configured to receive a signal including symbols carrying bit values in respective symbol intervals, and to convert the received signal into a serial sequence of digital samples, the received signal being modulated using a Differential Manchester Encoding (DME) scheme that (i) represents a first bit value by a first symbol type having a level transition in the corresponding symbol interval and (ii) represents a second bit value by a second symbol type having a constant level in the corresponding symbol interval. The processor is configured to derive an error signal from the digital samples, and to produce a quality measure of the received signal based on the derived error signal.
    Type: Grant
    Filed: February 20, 2022
    Date of Patent: October 24, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Shaoan Dai, Xing Wu, Wensheng Sun, Liang Zhu
  • Patent number: 11799578
    Abstract: This is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: October 24, 2023
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangye Wei, Liming Xiu, Yiming Bai
  • Patent number: 11800469
    Abstract: This application provides a communication method and a communications device. One example method includes: receiving, by a first communications device, first information from a third communications device; and sending, by the third communications device, the first information to the first communications device.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: October 24, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Feng Yu, Bo Lin, Guangwei Yu, Jiangwei Ying
  • Patent number: 11790368
    Abstract: An example operation may include one or more of computing historical patterns related to fraudulent attempts from a transaction log, predicting future fraud attempts from public data, correlating the historical patterns and the predicted future fraud attempts, modifying one or more endorsement policies based on the correlations, and adding the modified one or more endorsement policies to a smart contract.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Shikhar Kwatra, Jeronimo Irazabal, Edgar A. Zamora Duran, Roxana Monge Nunez, Sarbajit K. Rakshit
  • Patent number: 11784849
    Abstract: A communication control device for a user station for a serial bus system. The communication control device controls a communication of the user station with at least one other user station of the bus system, and generates a transmission signal for transmission onto a bus of the bus system and/or to receive a signal from the bus. The communication control device generates the transmission signal according to a frame in which bits having a predetermined temporal length are provided. The communication control device is designed to shorten, in comparison to some other bit of the bit sequence, at least one bit in the frame that is situated in a bit sequence of at least two bits having the same logical value, and the communication control device is designed to not shorten bits that are not situated in a bit sequence of at least two bits having the same logical value.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 10, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Simon Weissenmayer
  • Patent number: 11782792
    Abstract: A device is provided to include: a transceiver configured to transmit and receive data; and a skip ordered set (SKP OS) control logic in communication with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and a data block to a link connecting to an external device and including a plurality of lanes. The SKP OS control logic is configured to increase or decrease transmission interval of the SKP OS based on a transmission history of the SKP OS, in response to an entry of the link to a recovery state that is used to recover the link from an error.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 10, 2023
    Assignee: SK HYNIX INC.
    Inventors: Yong Tae Jeon, Dae Sik Park, Jae Young Jang
  • Patent number: 11784619
    Abstract: A circuit includes a first system-on-chip (SoC) driven by a first clock generator and a second SoC driven by a second clock generator where the first clock generator and the second clock generator have independent time bases. The first and second clock generators are synchronized using an RLC circuit external to the first clock generator and the second clock generator that converts an output of the first clock generator into current pulses and injects the current pulses into the second clock generator to pull an output of the second clock generator into synchronization with the output of the first clock generator. The RLC circuit converts a voltage output of the first clock generator into current pulses at the resonant frequency or specific harmonics of the output of the first clock generator. The second clock generator may include a ring oscillator into which the current pulses are injected.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: October 10, 2023
    Assignee: Snap Inc.
    Inventors: Jason Heger, Gerald Nilles
  • Patent number: 11777765
    Abstract: A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: October 3, 2023
    Assignee: Realtek Semiconductor Corporation
    Inventors: Hsu-Jung Tung, Lien-Hsiang Sung
  • Patent number: 11765410
    Abstract: Systems and methods for synchronizing the playback of OTT or other time sensitive content on multiple playback devices is disclosed. The systems and methods include receiving time information based on a network time source in the playback devices. The playback clock in each playback device is set based upon the time information. Stream initiation information derived using the time information from the network time source is received by each of the playback device from the media provider. The playback devices use the stream initiation information to adjust the presentation time stamps of the frames of the media content in the stream.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: September 19, 2023
    Assignee: DIVX, LLC
    Inventors: William David Amidei, Jason Braness
  • Patent number: 11765735
    Abstract: Provided is a method for designing downlink control channel for satisfying requirement of the different usage scenarios from each other in a next-generation/5G radio access network which has been discussed in the 3rd generation partnership project (3GPP). In particular, a method of a base station may be provided for transmitting/receiving data in a next-generation radio access network. The method may include configuring a time domain scheduling unit made up of at least one OFDM symbol for each user equipment, allocating a downlink data channel transmission resource with the time domain scheduling unit for a first user equipment, and puncturing a part of the downlink data channel transmission resource for the first user equipment and allocating the punctured resource to the downlink data channel transmission resource for a second user equipment.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: September 19, 2023
    Assignee: KT Corporation
    Inventors: Kyujin Park, Woo-jin Choi
  • Patent number: 11750698
    Abstract: A network device synchronization method is provided. In various embodiments, a first SSM and a second SSM are received. The first SSM carries a first SSM code indicating a quality level of a first clock source and a first eSSM code indicating the quality level of the first clock source, the second SSM carries a second SSM code indicating a quality level of a second clock source. The second SSM lacks an eSSM code indicating the quality level of the second clock source, and a value of the first SSM code is equal to a value of the second SSM code. When a value of the first eSSM code is less than 0xFF, calibrating a frequency of the network device based on a timing signal of the first clock source.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 5, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jingfei Lv, Yawei Zhang
  • Patent number: 11740652
    Abstract: A method for synchronizing clocks of at least two devices in a distributed network of a vehicle, comprising: establishing unencrypted communication between the at least two devices to determine a temporal difference between the clocks of the two devices, exchanging messages between the at least two devices via the unencrypted communication, ascertaining a temporal difference between the clocks of the at least two devices using the messages, establishing encrypted communication between the at least two devices to authenticate the exchange of messages, authenticating the messages that were used to ascertain the temporal difference, using the ascertained temporal difference, when the authentication of exchanged messages has been completed successfully.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 29, 2023
    Assignee: VOLKSWAGEN AKTIENGESELLSCHAFT
    Inventors: Arul Matheswaran, Jürgen Elberich, Rijo Varghese
  • Patent number: 11743848
    Abstract: Aspects provide for wireless communication between a UE and a radio access network (RAN) node in a wireless communication network. The RAN node may generate a re-synchronization signal (RSS) for a bandwidth part (BWP) of a plurality of BWPs and transmit the RSS in the BWP of a downlink to the UE. A first bandwidth of the RSS may be based on a second bandwidth of the BWP. The UE may receive the RSS in different RRC states and perform a measurement of the RSS for synchronization, for an early detection of a paging or wake-up signal, and/or for radio resource management (RRM) measurements or radio link monitoring (RLM) measurements. The UE may utilize a communication link with the RAN node based on the measurement and the RAN node may utilize the communication link to communicate with a group of UEs sharing at least one same RSS beam.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 29, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Lei, Wanshi Chen, Krishna Kiran Mukkavilli
  • Patent number: 11729036
    Abstract: Disclosed is a method and apparatus for transmitting and receiving a synchronization signal and a transmission system. In the method, a transmitting node determines a frequency band range in which a carrier is located, and configures or assumes synchronization channel information on the carrier according to the frequency band range, where the synchronization channel information includes at least one of: a subcarrier spacing or orthogonal frequency division multiplexing (OFDM) symbol information of a synchronization channel; and the transmitting node transmits the synchronization signal using the synchronization channel information.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 15, 2023
    Assignee: ZTE Corporation
    Inventors: Wei Gou, Feng Bi, Peng Hao, Junfeng Zhang
  • Patent number: 11711159
    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
  • Patent number: 11704021
    Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Shinichi Kanno
  • Patent number: 11689347
    Abstract: A communication system (500) includes a plurality of communication apparatuses (100) and selects from the plurality of communication apparatuses (100), a grandmaster that is to be a standard of time. A difference calculation unit (110), when receiving a synchronization message that includes time of the grandmaster from the grandmaster, calculates a time difference between the time of the grandmaster and time of the communication apparatus (100). A correction unit (120) changes count speed of a time counter that counts the time of the communication apparatus (100) in a way that the time of the communication apparatus (100) synchronizes with the time of the grandmaster at a time when a time correction period that is specified beforehand elapses, based on the time difference.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: June 27, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Taichi Sakaue