Abstract: A method for uplink burst equalization in broad wide access system, using the form of combining pre-training and burst equalization, that is, before transmitting user data, training the equalizer, then starting transmitting user data, in which, the equalizer uses decision user data as reference to track the changed wireless channel; if the change of channel exceeds the tracking region of equalizer, for example, the error rate exceeds threshold 1 but doesn't exceed threshold 2, the burst equalization will be performed; if the channel change exceeds the equalization region of equalizer, for example, the error rate exceeds threshold 2, the training will be performed again.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: A method determines tap coefficients of a phase interpolation finite impulse response (FIR) filter with respect to a digital-signal phase-locked loop processing apparatus including an A/D converter receiving a reproduced signal serving as digital data and sampling the received reproduced signal at a frequency higher than a data rate frequency and a PLL portion performing phase locking of the reproduced signal by filtering the sampled reproduced signal obtained by the A/D converter using the phase interpolation FIR filter and outputting a data sequence of the phase-locked reproduced signal. The method includes providing an adaptive equalization FIR filter at the data rate frequency at a stage subsequent to the PLL portion and determining the tap coefficients of the phase interpolation FIR filter using, as estimated values, FIR filter tap coefficients of the adaptive equalization FIR filter, which are converged so as to achieve a minimum mean square error.

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract: A filter equalization technique for an analog signal path, such as in an instrument that simultaneously measures a signal over a band of frequencies, uses magnitude measurement data for high frequency bands for which phase-calibrated sources are not readily available. A sinusoidal signal source together with an accurate power meter is used to provide a stepped frequency input over a desired frequency band to the analog signal path with an accurate measured magnitude. The output of the analog signal path is digitized and the resulting frequency magnitudes are computed. Then the resulting power meter results are deducted from the frequency magnitudes measured each time by the instrument to determine the magnitude response of the analog signal path. Using a Hilbert transform the corresponding phase response is determined based on a minimum phase assumption over the desired frequency band. From the magnitude and phase responses an inverse or digital equalization filter may be designed for the analog signal path.

Abstract: An apparatus for improved reception of a signal is described. The apparatus includes an equalizer that has at least two cascaded maximum-likelihood detectors and an adjustable delay unit. The equalizer and the adjustable delay unit are configured for adaptation in accordance with one or more multi-path signals in a communication channel that conveys the signal.

Abstract: A communication system includes a channel shortening filter to reduce intersymbol interference and facilitate recovery of communications. The channel shortening filter preferably includes a energy concentration filter that optimizes SNR or SINR or other performance criterion and a impulse response tail canceller filter that eliminates energy or, equivalently, cancels coefficients outside the allowed delay-spread window for the channel. Preferably the filters are calculated using signal decomposition.

Abstract: An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

Abstract: Methods and systems for reconfigurable soft-output bit demapping, reconfigurable for different modes of operation (i.e., different transmitter/receiver configurations) and for different modulation schemes are provided. In an embodiment, a reconfigurable soft-output bit demapping system includes a mode/modulation independent equalizer, a plurality of mode/modulation independent soft-slicers coupled to the outputs of the equalizer, a plurality of mode/modulation independent post-scalers coupled to the outputs of the soft-slicers, and a mode-dependent coefficient calculator. The coefficient calculator generates parameters for configuring the equalizer, the soft-slicers, and the post-scalers according to the used mode of operation and modulation scheme.

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract: The present invention is related to channel identification, equalizer initialization, and framing synchronization of GB 20600-2006 digital television signals. In one embodiment, the present invention provides, in a communications receiver having an equalizer that processes GB 20600-2006 digital television signals that include payload data, a method that initializes the equalizer coefficients for processing the payload data comprising: identifying a channel estimate based on correlation techniques; producing known, mock received data and filtering the mock, received data through the channel estimate to produce mock filtered data; adjusting the equalizer coefficients with the mock received data or the mock filtered data to obtain an initial equalizer setting; and processing the payload data with the initial equalizer setting.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: The invention relates to the installation of a broadcast data receiver or similarly installable apparatus. The apparatus and method of the invention includes a means for taking measurements to indicate whether the receiver is installed and operating to provide an optimum service to the user. The Broadcast Data Receiver (BDR) is provided with the processing and control capacity to undertake the comparison of the measured values of the incoming frequency signals at two spaced points and compare with predetermined parameters. If the comparison is acceptable, an indication is provided to the installer but if not the control system for the BDR adjusts of the operation of one or a plurality of components provided as part of a circuit within the BDR until the values are acceptable.

Abstract: A nonlinear equalizer for treating the nonlinear component of a distorted digital signal includes a first processing unit adapted to receive the distorted digital signal and yield an appropriate output signal in response thereto, a second processing unit adapted to receive the distorted digital signal and yield an appropriate output signal in response thereto, and a summation module for summing together the output signals from the first and second processing units so as to yield an equalized digital signal. In one embodiment, each of the first and second processing units comprises a linear filter, a partitioning filterbank for partitioning the distorted digital signal, and a multiplier for multiplying together the output of said linear filter with the output of said partitioning filterbank. In use, the nonlinear equalizer can be used to adaptively partition the distorted digital signal so as to allow for nonlinear equalization in a highly efficient manner.

Abstract: There is provided an apparatus and method for initializing a tap coefficient of an adaptive equalizer constituting a read path for a storage medium, where the apparatus includes an FIR filter, a Viterbi decoder, a level error detector, and a tap coefficient updater, the FIR filter receives a first signal stream and outputs the first signal stream in the form of a second signal stream, the Viterbi decoder corrects a bit error of the second signal stream, the level error detector detects a level error between the second signal stream and a third signal stream that is an ideal output signal corresponding to the second signal stream, the tap coefficient updater selects a tap coefficient minimizing the level error and provides the selected tap coefficient as a tap coefficient of the FIR filter, the tap coefficient minimizing the level error is determined as an initial value in a system initialization mode, and the determined initial value is used as an initial value of the tap coefficient of the FIR filter in a no

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Abstract: A method and apparatus for equalizing a reflection in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a compensating pulse that is transmitted in response to a pulse transmitted on the serial link. The apparatus comprises a programmable delay element and a driver stage configured to transmit a delayed and amplitude adjusted version of a pulse transmitted on the serial link. A method for equalizing a plurality of reflections in a reflective high speed serial link. The method involves obtaining an amplitude and delay time of a first compensating pulse and an amplitude and delay time of a second compensating pulse. The method further involves transmitting the first compensating and second compensating pulses in response to a pulse transmitted on the serial link.

Abstract: Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract: A channel dispersion estimation algorithm(s) may be implemented within a channel length estimation module of a multi-branch equalizer processing module that disables a branch of the multi-branch equalizer processing module when the channel length or channel delay spread associated with received radio frequency (RF) bursts exceeds a predetermined threshold. The channel dispersion estimation algorithm identifies when the radio frequency (RF) bursts have a channel length or channel delay spread that can affect receiver performance. The channel length estimation module may disable interference cancellation by a branch of the multi-branch equalizer processing module in response to such a channel length or channel delay spread.

Abstract: The invention provides a method of detecting high-mobility state of mobile terminal, comprising steps of: estimating a channel impulse response (CIR) based on received signal samples; performing channel equalization based on said received signal samples and the estimated channel impulse response; computing at least one characteristic value for a particular region of a relevant time slot based on the equalized signal samples; and deciding if said at least one characteristic value satisfies a predetermined condition that mobile terminal is in high-mobility state. The invention also provides a corresponding apparatus comprising: a channel estimator; a channel equalizer; computing means for computing at least one characteristic value for a particular region of a relevant time slot based on the equalized signal samples; and deciding means for deciding if said at least one characteristic value satisfies a predetermined condition of mobile terminal being in high-mobility state.

Abstract: An exemplary embodiment of an adaptive equalizer is provided, receiving symbols to generate an equalizer output. The adaptive equalizer comprises a plurality of tap cells, a coefficient updater, a plurality of multiplexers, a controller and an integrator. Each tap cell generates a filter value from a tap data value and a coefficient. The coefficient updater provides a coefficient vector comprising a plurality of coefficients updated recursively. Each multiplexer is coupled to a corresponding tap cell and the coefficient updater, switching between a normal mode and an estimation mode. The controller coupled to the multiplexers controls mode switching of each multiplexer based on each corresponding coefficient. The integrator coupled to the tap cells collects the filter values to generate an equalizer output.

Abstract: A method applied to an equalizer includes receiving an input data-stream having a training sequence component with a first number of symbols and a data component with a second number of symbols, wherein the first number plus the second number equals a third number; when a symbol number is not greater than the first number, training the training sequence component to generate a first trained coefficient set; when the symbol number is between the first number and the third number, recycling the training sequence component to generate a recycled training sequence component, and training the recycled training sequence component to generate a second trained coefficient set; storing the input data-stream to generate a delayed input data-stream when the symbol number is not greater than the third number; and applying the second trained coefficient set to the equalizer when the symbol number is greater than the third number.

Abstract: The present invention provides a multi-branch equalizer processing module operable to cancel interference associated with received radio frequency (RF) burst(s). This multi-branch equalizer processing module includes both a first equalizer processing branch and a second equalizer processing branch. The first equalizer processing branch is operable to be trained based upon known training sequences and equalize the received RF burst. This results in soft samples or decisions which in turn may be converted to data bits. The soft samples are processed with a de-interleaver and channel decoder, where the combination is operable to produce a decoded frame of data bits from the soft samples. A re-encoder may re-encode the decoded frame to produce re-encoded or at least partially re-encoded data bits. An interleaver then processes the at least partially re-encoded data bits to produce and at least partially re-encoded burst.

Abstract: The present invention provides a system and method for performing ranging operations in a cable modem system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modem system.

Abstract: A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

Abstract: Systems and methods for performing joint demodulation using a Viterbi equalizer having an adaptive total number of states are disclosed. Generally, a method includes joint demodulating a desired signal and none or more interfering signals with a Viterbi equalizer having an adapative total number of states based on channel impulse response (CIR) coefficients associated with a desired signal ant the one or more interfering signals.

Abstract: A test circuit to test an equalizer is disclosed. Pseudo-random number data is generated by a pseudo-random number data generation unit. A weight coefficient is generated by a weight coefficient generation unit in order to set interference strength of intersymbol interference. In a pseudo-intersymbol interference data generation unit, pseudo-intersymbol interference is generated according to a bit sequence of the pseudo-random number data, and pseudo-intersymbol interference data is outputted. An amplitude of the pseudo-intersymbol interference data is changed according to the weight coefficient. A driver converts the pseudo-intersymbol interference data into a differential signal. A comparison unit compares the pseudo-random number data generated by the pseudo-random number data generation unit with output data obtained from the equalizer, when the differential signal outputted from the driver is inputted into the equalizer. A count unit counts the number of unmatched data detected by the comparison unit.

Abstract: A method and system for decoding data received from a channel experiencing two-dimensional inter-symbol interference, as well as systems implementing such a decoding method and system, are disclosed. The method includes an iterative multi-strip equalization method that receives a plurality of channel values associated with a plurality of locations in a plurality of rows of a matrix, computes initial probability values based upon those channel values, applies a BCJR algorithm to symbol probability values based upon bands of rows of the initial probability values, and resolves the results of applying the BCJR algorithm to arrive at a plurality of bands of rows of revised probability values, which are subsequently combined/substituted with one another. The process iteratively repeats until the revised probability values attain a sufficient degree of convergence. By utilizing data from overlapping bands to perform the BCJR algorithm, ISI in both dimensions is addressed.

Abstract: A method and apparatus for equalizing digital data signals is disclosed. The method comprises the steps of demodulating and decoding an input signal having input data to produce a data output, remodulating the data output to produce a training sequence including an idealized input signal, wherein the training sequence is comprised of adjacent symbols in the input data, and generating equalizer parameters from the training sequence. The apparatus comprises a demodulator (for demodulating an input signal to produce a data output), a modulator communicatively coupled to the demodulator (for remodulating the data output to produce a training sequence including an idealized input signal wherein the training sequence is comprised of adjacent symbols in the input data), and a parameter generation module communicatively coupled to the modulator (for generating equalizer parameters from the training sequence).

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

Abstract: A receiver may train its equalizer using consecutive pilot bursts, divide the traffic between the consecutive pilot bursts into multiple sub-segments, and interpolate the trained equalizer coefficients to obtain the coefficients for equalizing one or more of the sub-segments. The receiver may also determine signal to interference and noise ratio (SINR) values based on each of the consecutive pilot bursts, and interpolate the SINR for decoding one or more of the sub-segments. The receiver may be an access terminal receiver operating in a code division multiple access (CDMA) cellular system.

Abstract: In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

Abstract: A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

Abstract: A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal.

Abstract: The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring device adapted to measure an operating environment of the modem; and a storage device adapted to store a list of PRBS generator definitions. The modem selects one of a plurality of PRBS generators based on the measurement of the operating environment.

Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.

Abstract: Method and apparatus for deciding a channel impulse response for an OFDM system are provided. First, a channel frequency response is generated by using a plurality of pilot tones of a signal. A channel impulse response is generated by applying the IFFT to the channel frequency response. A plurality of selected channel taps are derived by comparing a plurality of channel taps related to the channel impulse response with a reference threshold. Finally, the channel impulse response is generated by calculating channel impulse respose according to the selected channel taps. This method calculates the channel impulse response in time domain and frequency domain so that the calculation complexity can be reduced, and the system efficiency can be enhanced.

Abstract: In one embodiment, the present invention includes a method communicating control information for an external adaptive equalization process for a channel coupled between a transmitter and a receiver from an external agent. In this way, the external agent may control tap settings of an equalizer based on feedback information from the receiver responsive to a data pattern generated and transmitted by the transmitter. Other embodiments are described and claimed.

Abstract: A system for providing multi-channel multi-mode QAM equalization and carrier recovery is provided. According to one exemplary embodiment, the system includes an equalization circuit and a carrier recovery circuit operating in a concurrent manner to provide equalization and carrier recovery. The equalization circuit and the carrier recovery circuit each have two operating modes, namely, an acquisition mode and a tracking mode. The carrier recovery circuit evaluates a phase detection error calculated based on signals obtained from the equalization circuit. Based on the evaluation of the phase detection error, the equalization circuit and the carrier recovery circuit are respectively directed to switch operating mode, if appropriate.

Abstract: In a multi-carrier system employing OFDM, for example DMT, an adaptive channel equalizer is normally used, operating in the frequency domain. The sampling clock is controlled so that the time delay between the transmitter and the receiver is effectively eliminated. If the information used to control the sampling clock is received from the equalized data stream, it will introduce an ambiguity between the operation of the channel equalizer and the mechanism used to control the sampling clock. Operation of the equalizer can mask an increasing time difference, between transmitter and receiver, which the sample clock controller should be tracking. The present invention eliminates the ambiguities in the operation of the equalizer and sample clock controller by preventing the equalizer accepting time differences which should be corrected by operation of the sample clock controller.

Abstract: A receiving device is provided that comprises: a channel estimator adapted to receive an input; and an equalizer adapted to receive the input and generate an equalized output, wherein the equalized output is used by the channel estimator for at least one subsequent channel estimation.

Abstract: Messages transmitted between a receiver and a transmitter are used to maximize a communication data rate. In particular, a multicarrier modulation system uses messages that are sent from the receiver to the transmitter to exchange one or more sets of optimized communication parameters. The transmitter then stores these communication parameters and when transmitting to that particular receiver, the transmitter utilizes the stored parameters in an effort to maximize the data rate to that receiver. Likewise, when the receiver receives packets from that particular transmitter, the receiver can utilize the stored communication parameters for reception.

Abstract: A continuous time equalizer for equalizing an input signal using a feedforward equalizer portion and a feedback equalizer portion is provided that includes: a slicer operable to make bit decisions on a combined output from the feedforward and feedback equalizer portions; an adaptive delay circuit operable to delay the combined output to form a delayed output; and a controller operable to control the delay provided by the adaptive delay circuit such that a first group delay through the slicer and a second group delay through the adaptive delay circuit in response to a sinusoidal form of the input signal are substantially equal.

Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.

Abstract: A system and method are provided for calibrating for an I/Q mismatch of a direct conversion receiver based on a random signal having a two-dimensional I versus Q trajectory, such as radio frequency (RF) noise. In general, the random signal is received and downconverted to a quadrature baseband signal having an in-phase component and a quadrature component. The variance of the in-phase component, the variance of the quadrature component, and the covariance of the in-phase component with the quadrature component are computed based on samples of the quadrature baseband signal. A correction matrix used to compensate for the I/Q mismatch of the receiver and/or I/Q mismatch including a gain mismatch and a phase mismatch of the receiver is then computed based on the variance of the in-phase component, the variance of the quadrature component, and the covariance of the in-phase component with the quadrature component.