Abstract: An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.

Abstract: An encoding apparatus includes a dividing unit that divides an input signal bit sequence into data blocks and an encoding unit that applies error correction encoding to the data blocks to generate code blocks decodable by repetitive decoding calculations for estimating the reliability of signal bits for a plurality of times and a generation unit that generates redundant bits by performing bit calculations between data blocks of each set combining the divided data blocks; and an output unit that outputs the generated code blocks and redundant bits.

Abstract: Systems, devices and techniques for processing received QPSK modulated optical signals include sampling the received signal at twice the baud rate, thereby producing samples that are then processed as 9-QAM symbols using a decision directed least squares optimization method. Data bits are then recovered from the resulting symbol estimates. The received optical signal may also include dual polarized signals for increased bandwidth capacity.

Abstract: An apparatus comprising a memory and a processor coupled to the memory, wherein the memory includes instructions that when executed by the processor cause the apparatus to perform the following receive an incoming signal at a sampling rate that is greater than a symbol rate associated with the incoming signal, replicate a plurality of data streams from the incoming signal, apply a plurality of fractional delays for the data streams, and perform an adaptive equalization on a plurality of data blocks generated from the data streams, wherein the fractional delay is applied to the data streams independently of the adaptive equalization, and wherein the adaptive equalization implements taps spaced at a fraction of a symbol interval associated with the incoming signal.

Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

Abstract: A circuit for reducing phase errors in a digital communication systems signal is provided. The circuit comprises a demodulator block, a feed-forward path, a feed-back path, and a slicer. The demodulator block generates a plurality of samples from the signal and determines for each sample a corresponding phase error. The feed-forward path is configured to reduce in the signal a high frequency component of the phase errors. The feed-back path configured to reduce in the signal a low frequency component of the phase errors. The slicer selectively forwards phase errors to the feed-forward path or the feed-back path based on a respective magnitude of the phase error when operating in a decision-directed mode.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A controller and methods for adaptively adjusting a dispersion compensation circuit in a receiver of a communication link are disclosed. The controller receives a signal from an error detector coupled to the receiver. The controller includes a logic engine that provides configuration information to the dispersion compensation circuit. The configuration information defines a digital filter in response to at least one tap constraint and at least one coefficient constraint. In an example embodiment, the logic engine generates a measure of residual inter-symbol interference and a measure of a noise enhancement penalty and iteratively provides a set of adjusted coefficient values that when applied in the digital filter will result in an equalized receiver output signal that minimizes a mathematical combination of the measure of the residual inter-symbol interference and the measure of the noise enhancement penalty.

Abstract: A receiver and a method for equalizing signals, the method includes: receiving input signals; sampling the input signals to provide oversampled samples; processing the oversampled samples to provide symbol spaced samples and to provide fractionally spaced samples that represent the oversampled samples; calculating taps of a fractionally spaced equalizer based on the symbol spaced samples; feeding the taps to the fractionally spaced equalizer; and filtering the fractionally spaced samples by the fractionally spaced equalizer to provide equalized samples.

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract: A symbol-timing recovery function of a receiver is provided with a signal combiner (465) coupled to a first receive branch with a first receive signal (10) and to a second receive branch with a second receive signal (20). The signal combiner (465) generates a combined signal (C) on the basis of the first receive signal (10) and the second receive signal (20). Further, a common timing error detector (470C) is provided. The common timing error detector (470C) is coupled to the signal combiner (465) and is configured to generate a common timing error signal (TEC) on the basis of the combined signal. A first digital symbol timing for the first receive signal (10) and a second digital symbol timing for the second receive signal (20) are recovered on the basis of the common timing error signal (TEC).

Abstract: An adaptive equalizer and an adaptive equalizing method are provided. The adaptive equalizer includes an adaptive equalizing unit, for adaptively equalizing an inputted signal to output the equalized signal; a coefficient updating unit, for updating a coefficient of a filter of the adaptive equalizing unit; a switching unit, connected between the coefficient updating unit and the adaptive equalizing unit and a monitoring device, for controlling on or off of the switching unit in accordance with the fact that a down sampling phase of the inputted signal or a down sampling phase of the equalized signal is within a predetermined range. When the switching unit is on, the coefficient updating unit is capable of updating the coefficient of the adaptive equalizing unit, and when the switching unit is off, the coefficient updating unit is incapable of updating the coefficient of the adaptive equalizing unit.

Abstract: Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.

Abstract: A communication receiver including a time domain receive filter to provide a filtered output, the filtered output including colored noise. The receiver also includes a frequency domain, fractionally-spaced equalizer (FSE) unit to receive the filtered output from the receive filter. The FSE unit determines a separate weighting factor for each subcarrier, and the weighting factor is determined based on a noise variance of the subcarrier.

Abstract: Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

Abstract: Disclosed are a receiving equalization device and a method thereof, the receiving equalization device including a subtracter to output a first output signal, an eye monitor block to obtain a sampling timing by using the output first signal, and a slicer to generate a sampling signal by sampling the first output signal based on the sampling timing, and to return the generated sampling signal to the subtracter via a feedback filter or an algorithm determining block.

Abstract: A method and apparatus for receiving data in high-speed applications wherein an analog-to-digital converter (ADC) samples a received signal and a data decoder implemented with a tree search algorithm detects the bits of the sampled data for timing recovery. In some embodiments, a Viterbi detector is implemented to provide accurate bit detection for data output while tree search detected data is used to determine the optimal sampling phase for the ADC. In some embodiments, after the phase acquisition stage of timing recovery has completed, the tree search decoder may decrease the rate of data detection to maintain phase tracking.

Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities.

Abstract: The described aspects include a user equipment (UE) apparatus and corresponding method of equalizing samples of received signals in wireless communication. A plurality of samples of a signal received in wireless communication can be obtained, and on-time samples and late samples of the plurality of samples are independently equalized to respectively generate equalized on-time samples and equalized late samples. In addition, a preference factor can be applied to at least the equalized on-time samples to generate preferred equalized on-time samples, which are combined with the equalized late samples to generate a set of equalized samples for decoding.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A controller and methods for adaptively adjusting a dispersion compensation circuit in a receiver of a communication link are disclosed. The controller receives a signal from an error detector coupled to the receiver. The controller includes a logic engine that provides configuration information to the dispersion compensation circuit. The configuration information defines a digital filter in response to at least one tap constraint and at least one coefficient constraint. In an example embodiment, the logic engine generates a measure of residual inter-symbol interference and a measure of a noise enhancement penalty and iteratively provides a set of adjusted coefficient values that when applied in the digital filter will result in an equalized receiver output signal that minimizes a mathematical combination of the measure of the residual inter-symbol interference and the measure of the noise enhancement penalty.

Abstract: Equalization techniques for compensating distortion associated with a communications channel are provided. In one aspect of the invention, a method/apparatus for equalizing an input signal received from a communications channel includes the following steps/operations. At least one sampling is generated from the received input signal based on a clock signal unrelated to a clock signal used to recover data associated with the received input signal. Distortion associated with the communications channel is then compensated for based on at least a portion of the at least one generated sampling.

Abstract: An adaptive finite-impulse-response filter includes a series of taps; each tap has a corresponding value of tap coefficient. Values of tap coefficients are calculated to minimize a system error function. The solution is under-constrained, and some values of tap coefficients can grow and cause overflow errors. Growth of tap coefficients is controlled by introducing tap leakage. Disclosed is a symmetric leakage algorithm, in which an updated value of the tap coefficient of a particular tap is based on the old value of the tap coefficient of the particular tap, on the old values of the tap coefficients of a set of taps preceding the particular tap, and on the old values of the tap coefficients of a series of taps following the particular tap.

Abstract: A receiver may be operable to receive a signal. A sequence estimation module of the receiver may generate estimated symbols corresponding to the received signal. The generating of the estimated symbols may use tap information associated with one or both of a pulse shaper via which the signal was transmitted and an input filter of the receiver. The sequence estimation module may generate a reconstructed signal based on the estimated symbols and the tap information. A feed forward equalizer (FFE) of the receiver may adapt a plurality of tap coefficients of the FFE based on the reconstructed signal. The signal may be equalized via the FFE. The adaptation of the tap coefficients of the FFE may be based on a least-mean-square (LMS) process for minimizing a mean square of the error signal. An output signal of the FFE may comprise a power gain compensation.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: An algorithm to detect single path channel conditions and reduce the span (number of taps) of the equalizer in order to mitigate the performance degradation caused by noisy equalizer taps is disclosed. The algorithm provides two novel components comprising single path scenario detection and single path scenario processing or (equalizer shortening). A single path scenario is detected when the energy concentrated in a single channel impulse response tap divided by the total energy of the taps exceeds a predetermined threshold. When a single path scenario is detected, only the equalizer taps within a variable window around the equalizer tap having concentrated energy are used to filter the received signal.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: The described aspects include a user equipment (UE) apparatus and corresponding method of equalizing samples of received signals in wireless communication. A plurality of samples of a signal received in wireless communication can be obtained, and on-time samples and late samples of the plurality of samples are independently equalized to respectively generate equalized on-time samples and equalized late samples. In addition, a preference factor can be applied to at least the equalized on-time samples to generate preferred equalized on-time samples, which are combined with the equalized late samples to generate a set of equalized samples for decoding.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: A chip equalization apparatus and method for selecting cluster signals from broadcast signals being continuously received in multi-path channels for extracting a plurality of cluster signals from among the received broadcast signals and using a plurality of chip equalizers each having a tap coefficient update part for updating the tap coefficients of the selected cluster signals when the equalization outputs are combined to compensate the broadcast signals and provide low power consumption and efficient equalization for use in a satellite broadcasting receiving system.

Abstract: Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

Abstract: An interface circuit inputting and outputting data and a clock that have multiple speeds is provided with an equalizer capable of changing a circuit parameter, a frequency detection part detecting a clock frequency, and a parameter calculation control part calculating an appropriate circuit parameter according to the clock frequency and controlling the equalizer. The frequency detection part detects at what frequency the interface circuit is operating presently and sends the frequency to the parameter calculation control part. The parameter calculation control part calculates the circuit parameter of the equalizer so that the interface circuit operates optimally at the detected frequency, and sets the circuit parameter to the equalizer. In this manner, since the circuit parameter of the equalizer in the interface circuit can be controlled appropriately according to the frequency of the input and output clock, optimum operation is always available.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: A communication receiver including a time domain receive filter to provide a filtered output, the filtered output including colored noise. The receiver also includes a frequency domain, fractionally-spaced equalizer (FSE) unit to receive the filtered output from the receive filter. The FSE unit determines a separate weighting factor for each subcarrier, and the weighting factor is determined based on a noise variance of the subcarrier.

Abstract: This invention relates to a demodulating apparatus and a demodulating method for demodulating an input signal more quickly than before when the channels of the input signal are inverted. A correlator 152 calculates a correlation value indicative of the correlation between a known delayed detection sequence made of symbols of correct delayed detection values of a known sequence inserted in the input signal and a received delayed detection sequence obtained through delay detection of the input signal. If the imaginary part of the correlation value is less than zero, a channel control section 132 switches the channels of the input signal before feeding the signal to a frame synchronization circuit 122. This invention can be applied illustratively to a satellite broadcast receiving apparatus.

Abstract: An integrated circuit having a filter apparatus for filtering a first symbol sequence is disclosed. The first symbol sequence has a predetermined symbol duration. The apparatus includes at least one delay device which is clocked in accordance with a clock, and configured to delay the first symbol sequence by a delay time. A relationship between the delay time of the delay device and a clock duration of the clocked delay device has a predetermined value which is not equal to the one.

Abstract: A receiver for receiving a data signal having a channel profile may include an equalizer, to which the data signal is feedable, the equalizer having a plurality of filters and a switching device coupled to the filters, a selection device, which is disposed such that it determines a first number and a second number in dependence on the channel profile, and the switching device is disposed such that it connects a number of linear filters corresponding to the first number to form a first overall filter and connects a number of linear filters corresponding to the second number to form a second overall filter.

Abstract: An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU1 through ECUm; and an adder ADD1 which adds the output data of the M calculation units ECU1 through ECUM and the amplitude data A[N] together so as to generate equalized amplitude data D[N]. A step response waveform RSTEP(t) for the transmission line is approximated by Expression RSTEP(t)=SSTEP(t)·(1?Sj=1:M fj(t)) using M (M is an integer of 2 or more) functions fj(t) (1?j?M) and a step waveform SSTEP(t) with the time t as an argument. The representative value of the function fj(t) in a range between T1 and T2 is represented by a function gj(T1, T2).

Abstract: Instability resulting from non-linear impairments is detected and an equalizer of an end device is reset. An equalization instability threshold is retrieved from a data storage device. An equalization parameter for the end device is monitored and, if the equalization parameter exceeds the equalization instability threshold, the equalizer is reset.

Abstract: A receiver and a method for equalizing signals, the method includes: receiving input signals; sampling the input signals to provide oversampled samples; processing the oversampled samples to provide symbol spaced samples and to provide fractionally spaced samples that represent the oversampled samples; calculating taps of a fractionally spaced equalizer based on the symbol spaced samples; feeding the taps to the fractionally spaced equalizer; and filtering the fractionally spaced samples by the fractionally spaced equalizer to provide equalized samples.

Abstract: An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication.

Abstract: The conventional decision feedback equalizer has a drawback that can't decide symbols correctly because a simple slicer is used as a symbol detector. A decision feedback equalizer as a symbol detector uses a Trellis Coded Modulation (TCM) decoder whose Trace Back depth is 1 (TBD=1), to thereby decide symbols correctly without decoding delay.

Abstract: Provided are an equalization apparatus and method of compensating a distorted received signal. The equalization apparatus includes: a filter unit removing inter-symbol interference (ISI) from a multi-channel signal that is received; and a zero-offset controller identifying a zero offset of the multi-channel signal and determining operating coefficients of the filter unit by reflecting the identified zero offset. A response filter, which reduces loss and noise, can be used, and the structure of the response filter can be simplified. In addition, channel characteristics are estimated in real time at an initial stage of data transmission and reception. Thus, an equalizer optimized for channel interference characteristics can be provided.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has a plurality of non-adaptive and adaptive filter taps with weighted coefficients and a tap order selection circuit for selecting the number and order of adaptive filter taps based on one of at least measured output power from the adaptive filter and signal modulation. A demodulator and decoder receives the filtered output signal and demodulates and decodes the signal to obtain the communications data.

Abstract: A communication system comprises a receiver, which may generate broadcast coefficients that represent the characteristics of a channel using the channel information encoded in the segment synchronization units. The receiver may also use the channel information encoded in both the segment synchronization units and the field synchronization units to accurately determine the characteristics of a long channel.

Abstract: Various embodiments of the present invention provide systems and methods for performing adaptive equalization. For example, various embodiments of the present invention provide methods for adaptive equalization that include providing a data processing system with an equalizer circuit (210) and a target filter circuit (265). The equalizer circuit performs equalization based at least in part on an equalizer coefficient (215). The methods further include generating an error (285) based upon a first output from the equalizer circuit and a second output from the target filter circuit. An inter-symbol interference component (295) is extracted from the error (285) and used to calculate an equalizer gradient (226). Based at least in part on the equalizer gradient (226), the equalizer coefficient (215) is calculated.