Abstract: Various embodiments of the present invention provide systems and methods for performing adaptive equalization. For example, various embodiments of the present invention provide methods for adaptive equalization that include providing a data processing system with an equalizer circuit (210) and a target filter circuit (265). The equalizer circuit performs equalization based at least in part on an equalizer coefficient (215). The methods further include generating an error (285) based upon a first output from the equalizer circuit and a second output from the target filter circuit. An inter-symbol interference component (295) is extracted from the error (285) and used to calculate an equalizer gradient (226). Based at least in part on the equalizer gradient (226), the equalizer coefficient (215) is calculated.

Abstract: An efficient baseband predistortion linearization method for reducing the spectral regrowth and compensating memory effects in wideband communication systems using effective multiplexing modulation technique such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. The present invention is based on the method of piecewise pre-equalized lookup table based predistortion, which is a cascade of a lookup table predistortion and piecewise pre-equalizers, to reduce the computational complexity and numerical instability for desired linearity performance with memory effects compensation for wideband transmitter systems.

Abstract: Complex adaptive methods for complex information processing employ optimal individual convergence factors for real and imaginary components of the weight vector. For wireless receivers operating on QPSK, a Complex IA-ICA performs better than existing Complex Fast-ICA methods in terms of accuracy and convergence speed, can process such complex signals in time-varying channels, and employs time-varying and time-invariant convergence factors, independent for the real and imaginary components of the system parameters, and provide individual or group system parameter adjustments. Such systems employ the within complex adaptive ICA with individual element adaptation (Complex IA-ICA).

Abstract: A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Abstract: A system and method for configuring an equalizer 48 for a transmission link includes a computer 82 that forms a mathematical model of an analog equalizer having a plurality of mathematical model filter stages. The computer 82 determines a desired response and tunes each of the plurality of mathematical model filter stages toward the desired response to form a plurality of model filter parameters to compensate for distortions in the transmission link. The equalizer 48 is coupled to the RF chain. The plurality of filter stages is tuned in response to the filter parameters. The RF signals are broadcast in response to analog equalizer.

Abstract: A communications system receives a modulated communication signal that carries encoded communications data. A signal input receives the communication signal. An adaptive filter circuit is connected to the signal input and comprises N number of parallel adaptive filters. Each adaptive filter has non-adaptive and adaptive taps with weighted coefficients that are different in number from the respective other parallel adaptive filters within the adaptive filter circuit. A selection output circuit is connected to each adaptive filter and selects for output the adaptive filter having the most suppression or least output power or other criterion which can indicate a best choice to use of the N parallel adaptive filters. A demodulator demodulates the signal and a decoder receives the filtered output signal from the demodulator and decodes the signal to obtain the communications data.

Abstract: A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract: The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter circuit has a plurality of adaptive filters each having a plurality of non-adaptive and adaptive filter taps with weighted coefficients. At a selected adaptive filter, an interference reduction circuit is responsive to one of at least a received state of a demodulator, the type of modulation used by communication system and the input and output power of adaptive filter for updating the adaptive gain of the adaptive filter, selecting the number and order of adaptive filter taps, separating the spacing of multipath introduced by adaptive filter, controlling input and output normalizing circuits to adaptive filter(s) and selecting if signal passed to demodulator is original received signal or signal output by adaptive filter. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract: Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.

Abstract: A waveform equalizing device for performing high-precision waveform equalization for an input signal and outputting the result as an output signal, includes: a FIR filter for performing convolution operation between the input signal and a plurality of tap coefficients; first and second slicers at least one of which makes decision on the value of the output signal; a first delay device for imparting a delay to the output of the second slicer; an IIR filter; and an addition section for summing the output of the FIR filter and the output of the IIR filter and outputting the sum as the output signal. The IIR filter includes first and second delay portions for respectively receiving the outputs of the first slicer and the first delay device and imparting delays, and performs convolution operation between the signal received by the first delay portion and tap coefficients for the first delay portion and between the signal received by the second delay portion and tap coefficients for the second delay portion.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

Abstract: An apparatus, computer software, and method for data detection in channels suffering from intersymbol interference comprising receiving a signal representative of a binary digit of data, computing a reliability score for that binary digit of data via windowed Chase equalization, and based on the reliability score, causing a signal to be output that the binary digit is a zero or a one.

Abstract: In accordance with the teachings described herein, an extended equalizer circuit is provided for equalizing a digital communication signal transmitted over a transmission medium that causes a frequency-dependent attenuation of the digital communication signal. An equalizer may be used that includes a linear equalization circuit and a non-linear equalization circuit, the linear equalization circuit being configured to apply a linear filter to the digital communication signal to compensate for the frequency-dependent attenuation caused by a first portion of the transmission medium, and the non-linear equalization circuit being configured to apply one or more non-linear operations to the digital communication signal.

Abstract: A system and method of adapting a FIR filter with a mixed minimum-mean-square-error/zero-forcing adaptation is disclosed. A channel response module attempts to approximate a noiseless component of the channel response. The output of the channel response module is utilized to adapt a FIR filter module. In some embodiments, a combination of the output of the channel module and the noiseless channel output is utilized to adapt the FIR filter. In some embodiments, a second FIR filter module is utilized to process the noiseless channel output, which is then compared to the target response to generate an error signal, which may be used to adapt both the first and second FIR filter modules.

Abstract: This disclosure describes equalization techniques for spread spectrum wireless communication. The techniques may involve estimating a channel impulse response, estimating channel variance, and selecting filter coefficients for an equalizer based on the estimated channel impulse response and the estimated channel variance. Moreover, in accordance with this disclosure, the channel variance estimation involves estimation of two or more co-variances for different received samples. Importantly, the equalizer is “fractionally spaced,” which means that the equalizer defines fractional filtering coefficients (filter taps), unlike conventional equalizers that presume that filter coefficients are defined at integer chip spacing. The techniques can allow the equalizer to account for antenna diversity, such as receive diversity, transmit diversity, or possibly both.

Abstract: A method and an apparatus for slicing an analog signal using an analog encoder.

Abstract: A decoding unit for decoding a modulated signal includes a summing unit having i) a first input, ii) a second input, and iii) an output. The summing unit is configured to i) receive the modulated signal at the first input, ii) receive a feedback signal at the second input, and iii) output a first waveform based on the modulated signal and the feedback signal. A demodulation unit has a first demodulation pathway and a second demodulation pathway. The demodulation unit is configured to i) select between the first demodulation pathway and the second demodulation pathway, ii) receive and demodulate the modulated signal with the first demodulation pathway, and iii) receive and demodulate the first waveform with the second demodulation pathway. The remodulation unit is configured to selectively i) output a first complex waveform based on the modulated signal, and ii) output a subsymbol waveform of the first waveform.

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.

Abstract: An optical transceiver and a method to setup the optical transceiver are disclosed, where the transceiver has a function to compensate the distortion and the dispersion due to the limited bandwidth of the electrical signal line, that of the active devices, and that of the optical fiber. The optical transceiver comprises a transmitter with an equalizer unit and a receiver also with an equalizer unit. The equalizer unit in the transmitter compensates the distortion due to the limited bandwidth of the transmission lines for the electrical signal and that of the semiconductor active device, while, the equalizer unit in the receiver compensates the dispersion due to the limited bandwidth of the optical fiber.

Abstract: The present invention relates to pre-distortion in transmitter circuits and provides a circuit for introducing pre-distortion into the output of a transmitter, wherein said pre-distortion comprises a pre-cursor, a cursor and a post-cursor, the circuit comprising: a first driver arranged to switch an output drive between said pre-cursor and said cursor; a second driver arranged to switch an output drive between said post-cursor and said cursor; a third driver arranged to switch an output drive between a positive cursor drive and a negative cursor drive. The arrangement provided give flexibility when setting the pre-cursor, cursor and post-cursor levels.

Abstract: A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further delaying a multilevel analog signal tapped from stage n, combining the further delayed signal from stage n with an analog error signal e(t) to provide an analog weighting function Wn, wherein the combining of the delayed signal from stage n with Wn results in a plurality of signals XnWn, summing the plurality of signals XnWn, slicing a multilevel analog signal resulting from the summing of the plurality of signals XnWn using one threshold level to generate the analog error signal e(t), and combining the delayed signal from stage n with Wn.

Abstract: Embodiments related to echo compensation have been described and depicted.

Abstract: An algorithm is provided that computes values for correcting for DC offsets of baseband I and Q signals, compensates for amplitude imbalance between the baseband I and Q signals and compensates for phase imbalance between the baseband I and Q signals. Test signals are injected into the I and Q signal processing paths (either or both of the receiver path and baseband path in a modem). Samples of the I and Q signals produced in the I and Q signal processing paths are generated and analyzed to determine DC offsets of the I and Q signals, amplitude imbalance between the I and Q signals and phase imbalance with respect to a desired orthogonal relationship between the I and Q signals.

Abstract: Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.

Abstract: A computerized system simulates a non-linear Decision Feedback Equalizer. The computerized system includes a user interface, an output port, and a controller coupled to the user interface and to the output port. The controller is configured to (i) receive electronic design automation commands from a user through the user interface, (ii) generate, as an electronic model of the non-linear Decision Feedback Equalizer, an electronic representation of a linear filter in response to the electronic design automation commands, and (iii) integrate the electronic representation of the linear filter into an electronic circuit design having other electronic representations of other electronic circuits. The electronic circuit design is externally accessible through the output port.

Abstract: Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.

Abstract: A channel estimator and a related method for smoothing channel responses of a multi-carrier system. The channel estimator includes a channel response computing circuit for computing at least one of a target channel estimation and a reference channel estimation by utilizing a computing algorithm, wherein the target channel estimation and the reference channel estimation corresponds to a sub-carrier channel respectively.

Abstract: A method to reduce peak power consumption during adaptation for an integrated circuit (IC) with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops.

Abstract: For a given channel and a filter having at least one filter tap, a set of at least one weight value is determined for the at least one filter tap according to which at least one weight value substantially minimizes a gradient of a frequency response for the given channel and substantially maximizes energy of the frequency response for the given channel within a predetermined bandwidth.

Abstract: A feedback equalizer includes a summing unit having an output and first input for receiving a modulated signal, which includes a symbol defined by a first number of chips. A subsymbol processor is coupled to the output of the summing unit. The symbol processor is capable of generating a subsymbol waveform upon receipt of a second number of chips of the symbol. The second number is less than the first number. A feedback filter is coupled to a second input of the summing unit and the symbol processing unit to selectively filter the subsymbol waveform from the modulated signal.

Abstract: A method and apparatus for a feed forward equalizer for a communication system are described. An equalizer comprising a tapped filter having multiple filter multipliers and a summing element is described. The equalizer further comprises a correlator having multiple correlator multipliers, with each correlator multiplier having a corresponding integrator, a set of shared delay elements to connect to the filter multipliers and the correlator multipliers; and an error signal generator to connect to the correlator.

Abstract: A method of optically equalizing a multi-level (amplitude or phase) optical signal through the effect of an optical equalizer wherein the optical equalizer (OEQ) is placed at either a transmission end or a receiver end of the optical communications link and a tap delay characteristic of the OEQ need not be determined by symbol spacing, rather it may advantageously be adjusted to desirably compensate non-linear mapping performed in the modulation process or simultaneous operation on a plurality of wavelength division multiplexed (WDM) channels.

Abstract: A second-order Volterra filter has a quadratic section including a plurality of multiplication units that multiply a first input signal with a second input signal. One of the multiplication units employs a signal not delayed from the first input signal, as the second input signal. A remaining one of the multiplication units employs a signal delayed a preset time from the first input signal, as the second input signal. The one of the multiplication units includes a multiplier that multiplies the signal output from the one of the multiplication units and a signal output from each of one or more delay units, each with a preset coefficient. A step gain parameter for updating each preset coefficient of a multiplier of the remaining one of the multiplication units is twice a step gain parameter for updating each preset coefficient of the multiplier of the one of the multiplication units.

Abstract: Exemplary embodiments of the present invention provide an equalizer combined with a decoder and a method of updating filter coefficients. The method may include calculating output error signals ek, multiplying the output error signals by a parameter, obtaining a partial value by multiplying a delayed decoder decision stored in a filter delay line corresponding to an i-th filter coefficient by the result obtaining a partial value by multiplying a constant by a feedback coefficient and obtaining an updated value by adding the two partial values.

Abstract: Disclosed is a mobile communication terminal which is provided with an equalizer function of audio equipment to adjust a timbre of transmitting/received speech sounds so as to satisfy a great number of users having various individualities and tastes simultaneously. The mobile communication terminal according to the present invention includes an equalizer connected to a CODEC, a speaker and a microphone for adjusting a timbre of an analog speech signal inputted thereto from the CODEC and/or a speech signal inputted thereto through the microphone, and an equalizer control circuit for controlling a timbre control operation of the equalizer according to a control signal of a CPU.

Abstract: A serial-parallel converter/encoder unit 11 inputs a transmission symbol data at a transmission symbol rate that is one-Nth of a base-point symbol rate. A precoder/collator 13 creates a transmission symbol waveform at the base-point symbol rate. The transmission symbol waveform becomes a transmission signal after passing through a roll-off filter 14 with a band corresponding to the base-point symbol rate and a modulator 15. A reception signal demodulated by a demodulator 33 is input to a fractionally-spaced equalizer 38 that operates at the base-point symbol rate and is forcibly equalized at the transmission symbol rate by using a reference signal. A level of a signal output from the fractionally-spaced equalizer 38 at the transmission symbol rate is determined by a level determining unit 39 and becomes a reception symbol data by a sawtooth-function output unit 40.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.

Abstract: A technique for arranging a receiver device (20) includes equally spacing adjacent rake receivers (26-30) within an observation window (OW). A disclosed technique for updating an observation window includes changing the position of one of the rake fingers (24, 30) while maintaining a position of other ones of the rake fingers. The disclosed technique for arranging rake fingers in a receiver device (20) does not depend on searching and tracking channel conditions and reduces computational complexity without sacrificing receiver performance.

Abstract: A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase error. The timing phase error is then averaged and controls a phase locked loop (PLL). This PLL in turn controls a voltage-controlled oscillator, which handles the modem receiver timing. A centroid calculation can be included to bias the voltage-controlled oscillator to push the equalizer coefficients back to the ideal position. The system can be implemented in either a point-to-point modem environment or a multi-point environment, for example, but not limited to, MVL or DMT. The voltage-controlled oscillator may also be implemented to control transmitter timing, so that the central office modem and the remote modem will operate more-or-less synchronously, reducing the need for large equalizer corrections at either end.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: There is provided a multi sub-carrier communication system for providing improved performance of a frequency equalizer and a method thereof. The multi sub-carrier communication system includes a frequency equalization coefficient (vector) calculation unit that receives an equalized signal outputted from a frequency equalizer and periodically calculates a new frequency equalizer coefficient (vector) which is used to update the frequency equalizer coefficient (vector) used by the frequency equalizer. The multi sub-carrier communication system periodically updates the frequency equalization coefficient (vector) (after an initialization interval for initially estimating a channel characteristic) by periodically calculating the frequency equalization coefficient (vector) during a data receiving interval and thus, it is possible to dynamically adapt to changes of the channel characteristic over the passage of time, thereby improving performance of the frequency equalizer.

Abstract: An adaptive equalizer comprises: a forward equalizer (FE) receiving a symbol stream to generate an FE output; a decision feedback equalizer (DFE) receiving a decision symbol stream to generate a DFE output; a first adder, coupled to the forward equalizer and the decision feedback equalizer, adding the FE and DFE outputs to generate an equalizer output; a first trellis decoder, coupled to the first adder, receiving the equalizer output to generate a trellis decoded stream by a trellis decoding process; and a compensator for compensating the equalizer output according to the decision symbol stream, the trellis decoded stream, and a coefficient vector stored in the decision feedback equalizer, to generate a compensated equalizer output.

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract: Disclosed are a system, method and device for generating an equalized signal from an input signal. Symbols in the equalized signal may be detected on each of a sequence of symbol intervals to recover a symbol value in the symbol interval. A feedback coefficient may be applied to a symbol value recovered in a previous symbol interval to generate the equalized signal in a current symbol interval. The feedback coefficient may be generated based, at least in part, on an estimated error associated with the equalized signal. The estimated error associated with the equalized output signal from among a plurality of candidate estimated error values.