Abstract: In described examples of a signal equalizer, a first filter stage is configured to perform adaptive equalization of crosstalk between a first signal component and a second signal component of a complex signal. A second filter stage is coupled serially to the first filter stage. The second equalizer stage is configured to perform separate adaptive equalization of the first signal component and separate adaptive equalization of the second signal component.

Abstract: Quadrature error correction (QEC) for radio transceivers are provided herein. In certain embodiments, a transceiver includes an in-phase (I) signal path including a first controllable amplifier coupled to a first data converter, and a quadrature-phase (Q) signal path including a second controllable amplifier coupled to a second data converter. The transceiver further includes a QEC circuit operable to correct for a quadrature error between the I signal path and the Q signal path by adjusting a gain of the first controllable amplifier and/or a gain of the second controllable amplifier.

Abstract: A Radio Frequency Impairments (RFI) compensator and a process to remove RFI is disclosed. The RFI compensator including: a conjugator to conjugate a signal {tilde over (x)}[n] to provide a signal {tilde over (x)}*[n]; and a filter to apply coefficients that equalize a linear distortion of the signal {tilde over (x)}[n] and reject an interfering image of the signal {tilde over (x)}*[n]. The signal {tilde over (x)}[n] maybe a single wideband carrier or may include multiple carriers at different carrier frequencies.

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

Abstract: A Radio Frequency Impairments (RFI) compensator and a process to remove RFI is disclosed. The RFI compensator including: a conjugator to conjugate a signal {tilde over (x)}[n] to provide a signal {tilde over (x)}*[n]; and a filter to apply coefficients that equalize a linear distortion of the signal {tilde over (x)}[n] and reject an interfering image of the signal {tilde over (x)}*[n]. The signal {tilde over (x)}[n] may be a single wideband carrier or may include multiple carriers at different carrier frequencies.

Abstract: Aspects of this disclosure relate to a VLIF receiver with automatic phase noise adjustment. The presence of an interfering signal is sensed within a bandwidth around a desired channel frequency. Then the local oscillator phase noise is automatically adjusted to optimize blocking. The phase noise adjustment includes increasing the bandwidth of a phase-locked loop.

Abstract: One example includes an equalizer system. The system includes a filter system configured to receive digital sample blocks associated with an input signal and to provide equalized digital sample blocks associated with the respective digital sample blocks based on adaptive tap weights. Each of the digital sample blocks includes samples and each of the equalized digital sample blocks includes equalized samples. The system also includes a sample set selector to select a subset of equalized samples from each of the equalized digital sample blocks at the output of the filter and an error estimator configured to implement an error estimation algorithm on the subset of the equalized samples to determine a residual error associated with the equalized samples. The system further includes a tap weight generator configured to generate the adaptive tap weights in response to the residual error and to provide the adaptive tap weights to the filter.

Abstract: Methods and apparatuses for performing synchronization in a receiver of an analog code division spreading system are described. The method includes outputting a sampling point alignment signal to apply first time delays to align encoder code signals with a sampling point of an ADC The ADC is used to obtain digital samples of the orthogonal code-encoded analog signal at the sampling point. The method also includes outputting a decoder code alignment signal to apply second time delays to align decoder code signals with the digital samples. The method also includes outputting an orthogonal code alignment signal to apply third time delays to the decoder code signals and the encoder code signals, to maintain mutual orthogonality among the decoder code signals and to maintain mutual orthogonality among the encoder code signals.

Abstract: In accordance with an embodiment, a method for operating a radio frequency (RF) transceiver includes frequency-translating, using a local oscillator signal having a calibrated phase shift, a signal received at an antenna of an RF transceiver; filtering the frequency-translated signal using a programmable filter of the RF transceiver to produce a filtered frequency-translated signal; and changing a cutoff frequency of the programmable filter from a first cutoff frequency to a second cutoff frequency in response to the RF transceiver switching operation from a first mode to a second mode.

Abstract: Methods for RSRP estimation in LTE networks that perform interference cancellation are provided. In particular, a bias that is present during interference cancellation is account for in the RSRP estimation of a target cell.

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

Abstract: Methods and apparatus for calibrating a polar transmitter are provided. Calibration circuitry is configured to generate an adjustment signal that communicates an amplitude modulation/phase modulation (AMPM) delay value to AMPM delay circuitry that is configured to delay, based at least on the AMPM delay value, output of a signal by digital signal processing circuitry (DSP) in the polar transmitter. The calibration circuitry includes signal generation circuitry, estimation circuitry, and delay circuitry. The signal generation circuitry is configured to generate a calibration signal to control the polar transmitter to generate a calibration transmit signal. The estimation circuitry is configured to receive a result signal that is based on the calibration transmit signal and estimate the AMPM delay value based at least on the result signal. The delay circuitry is configured to provide an adjustment signal to communicate the estimated AMPM delay value to the AMPM delay circuitry.

Abstract: A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

Abstract: A method and apparatus for improving performance in communication systems is provided. In one implementation received encoded data is decoded using an inner rateless decoder to produce a series of decoded rateless outputs. The series of decoded rateless outputs is combined to produce a block, and the block is decoded using an outer block decoder. In another implementation, encoded data for a data block encoded with a rateless code is received. It is determined that an initial amount of mutual information for the data block has been received, the initial amount being an amount expected to allow decoding of the received encoded data. Additional encoded data for the data block is received. It is determined that an extra amount of mutual information for the data block has been received beyond said initial amount of mutual information.

Abstract: There is provided an apparatus allowing waveform shaping even at a low sampling rate, which includes a sampling unit, an equalizing unit, a tap coefficient calculating unit, a delay adjusting unit, a peak monitoring unit, and a timing value extracting unit. The timing value extracting unit provides a magnitude of a delay to the delay adjusting unit, and from a plurality of sets of the magnitude of the delay provided by the delay adjusting unit and maximum values of output signal intensity acquired by the peak monitoring unit, acquires the magnitude of a delay where the output signal intensity becomes the greatest, as a suitable delay amount, and notifies the delay adjusting unit of the suitable delay amount.

Abstract: A blind equalizer apparatus includes a decision-directed (DD) least mean squares (LMS) blind equalizer. A blind equalizer apparatus includes: a DD LMS blind equalizer, wherein: the blind equalizer uses a finite impulse response filter with tap weights that are adaptively updated using a filter tap update algorithm, wherein blind equalization of one of an in-phase (I) channel and a quadrature (Q) channel is carried out by maximizing the Euclidean distance of binary modulated waveforms, wherein the blind equalizer averages a block to compute an independent phase estimate for a block, wherein the blind equalizer computes an error variable for a block from the phase estimate for the block, wherein the blind equalizer uses the phase estimate and alternating I/Q one dimensional/binary slicing to make a hard decision, and wherein the blind equalizer uses the hard decision to derive an error variable that is used to update the filter tap weights.

Abstract: Spatial Multiplexing (SM) with Multiple Input Multiple Output (MIMO) is used in many communication systems for providing high data rates. While SM-MIMO is a powerful technique for increasing the data rate and bandwidth efficiency, the decoders for SM-MIMO are highly complex. The complexity grows exponentially for optimum decoders as the number of multiplexed layers in SM-MIMO increases. Many reduced complexity suboptimal methods are used in practice that have close to optimum performance but they remain highly complex causing high power consumption which is not desirable for battery operated client terminals. Due to the parallel architecture of many of the SM-MIMO decoders, they involve computations that may eventually turn out to be redundant. A method and apparatus may include identifying and eliminating potentially redundant computations in SM-MIMO decoders based on the technique referred herein as precomputation. The removal of redundant computations enables reduced power consumption for SM-MIMO decoders.

Abstract: A system and method for decision feedback equalization of a crossing slicer. A serial receiver includes a data slicer and a crossing slicer, and implements decision feedback equalization for the data slicer, with a plurality of data weights. The serial receiver also implements decision feedback equalization for the crossing slicer, using crossing weights that are interpolated between corresponding pairs of the data weights. The crossing weights may be formed by any suitable interpolation method, including linear interpolation, cubic interpolation, or spline interpolation.

Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.

Abstract: The present invention concerns a method and associated apparatus for reducing the time required to scan an incoming satellite transmission power spectrum for available signals and to determine the characteristics of those signals. The frequency range of interest is scanned in narrow slices to determine approximate input power within each slice. Center frequencies and symbol rates of individual transponders are then estimated based upon these input power approximations.

Abstract: A method and system for compensating for frequency dependent phase and amplitude imbalances is provided. A plurality of frequency sub-bands is extracted from a received wideband signal. Each of the plurality of frequency sub-bands is compensated to produce an associated plurality of compensated frequency sub-bands. The compensated sub-bands are summed in order to produce a compensated signal.

Abstract: Briefly, in accordance with one or more embodiments, a platform may comprise a receiver to receive a signal that includes an error in the received signal due to a noise signal generated in the platform, and a processor configured to calculate a noise vector from a source of the noise signal and to send the noise vector to the receiver, The receiver may include a digital signal processor configured to estimate an error vector based at least in part on the noise vector and to subtract the estimated error vector from the received signal to cancel the noise signal from the received signal. The noise cancelled from the received signal may include platform noise generated by a bus, a memory circuit, a clock, a power supply, a circuit ground or integrated circuit substrate, or input/output circuit of the platform.

Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

Abstract: A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal.

Abstract: A method and an apparatus for modifying a complex-valued signal are described, the complex-valued signal representing a first symbol and a second symbol. A signal trajectory of the complex-valued signal between the first and second symbols is determined, and, if the signal trajectory passes nearby the constellation origin, the signal trajectory is altered to run closer to the constellation origin.

Abstract: Embodiments of the present invention provide an apparatus comprising a transceiver having a receiver and a transmitter connected through a segment of a calibration loop back path. The apparatus also comprises a control system configured to communicate with the transceiver. The calibration loop back path has an intentional phase shift that can be toggled between an off state and an on state by the control system. The control system is configured to calculate the intentional phase shift by examining the difference of a first and second phase angle. The first phase angle is obtained from the transmission of a first pair of signals with the intentional phase shift in the off state. The second phase angle is obtained from the transmission of a second pair of signals with the intentional phase shift in the on state.

Abstract: An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.

Abstract: Methods, systems, and apparatuses are described for compensating for impairments of a wireless device. In accordance with a disclosed method, a set of equalizer taps for an analog pipeline of the wireless device is determined. A first set of complex filter taps and a second set of complex filter taps are also determined, by modifying the set of equalizer taps according to an estimated imbalance of the analog pipeline of the wireless device. A signal associated with the analog pipeline is processed with a complex filter according to the first set of complex filter taps and the second set of complex filter taps. The processing provides a combined imbalance compensation and equalization of the signal. The complex filter may include a first complex half-filter associated with the first set of complex filter taps and a second complex half-filter associated with the second set of complex filter taps.

Abstract: A system for balancing a signal having I and Q components includes means for cross correlating the I and Q components to produce a cross correlation product; means for adjusting the gain of each I and Q signal component in accordance with said cross correlation product; and means for adding one component with the adjustable gain of the other component to produce a phase-balanced signal.

Abstract: Disclosed herein are systems and methods for accurate removal of I/Q mismatch in received signals of an analog FM receiver. The analog FM receiver includes a down-converter, a calibration circuit that estimates I/Q mismatch values, and a compensation circuit that uses the estimated mismatch values to reduce the effects of I/Q mismatch. In one aspect, the calibration circuit uses an adaptive dual-parameter compensation scheme to iteratively correct the received signals by approximating a coefficient value and an amplitude value that minimize the signals' amplitude variation from the amplitude value. In another aspect, phase and amplitude mismatch parameters can be determined using the coefficient value.

Abstract: A system and method are disclosed for coordinating the scheduling of beamformed data to reduce interference in a wireless system. A customer premise equipment (CPE) uses a plurality of bits to quantize the phase angle of the beamformed data received by CPE and reports it to its serving base station. The serving base station selects one of the phase adjustment angles based on the bits received from the CPE in order to schedule the data transmission to the CPE. The phase adjustment angles are in “n” degree steps.

Abstract: Disclosed are a receiving equalization device and a method thereof, the receiving equalization device including a subtracter to output a first output signal, an eye monitor block to obtain a sampling timing by using the output first signal, and a slicer to generate a sampling signal by sampling the first output signal based on the sampling timing, and to return the generated sampling signal to the subtracter via a feedback filter or an algorithm determining block.

Abstract: A method of determining non-ideality characteristics introduced on a signal by a transceiver is disclosed. The transceiver has an up-conversion transmitter and a down-conversion receiver. In one aspect, the method includes: a) generating a signal comprising at least one known training symbol, b) up-converting this signal with a first frequency to a first signal in the transmitter, c) transferring the first signal from the transmitter to the receiver, d) down-converting with a second frequency this transferred first signal to a second signal in the receiver, the second frequency being different from but linked to the first frequency, e) detecting at least one of the training symbols in the second signal; and f) separating, in the frequency domain, at least one of the components of at least one of the detected training symbols for determining the non-ideality characteristics.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.

Abstract: A calibration technique to compensate for the phase error between the in-phase and quadrature sampling clocks controlling the quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) is provided. A low-frequency test tone is injected, up-converted to the RF frequency, and added to an input of the QBS-ADD. The test tone is demodulated by the QBS-ADD into an in-phase signal and a quadrature signal. The in-phase and quadrature signals are filtered and multiplied together to generate a phase error signal, which is subsequently integrated to generate a phase shift control signal being used to correct the phase error between the in-phase and quadrature sampling clocks.

Abstract: A signal processing apparatus includes a signal processing unit configured to carry out signal processing on a single-carrier signal and a multi-carrier signal by making use of a plurality of common filters shared by the single-carrier signal and the multi-carrier signal.

Abstract: A signal detection apparatus detects the frequency of an input signal without using a PLL. The detection apparatus includes a first and a second orthogonalizer, a phase difference calculator and an integrator, to control the variable coefficient a1 of a band-pass filter. Information e[k]=M·sin(?) representing the phase difference ? between the input data x[k] and the output data y[k] is calculated with the first and second orthogonalizers and the phase difference calculator. The sign of e[k] is inverted and a predetermined integral calculation is performed with the integrator, and the calculated integral value is set as the coefficient a1 of the band-pass filter. Every time input data x[k] is input, the coefficient a1 is changed by reducing it when e[k]>0 and increasing it when e[k]<0. Thus, the frequency of the output signal of the band-pass filter is matched to the input signal.

Abstract: The teachings presented herein allow the same sequence of local oscillator waveform sample values to be used for driving two harmonic rejection mixers for which quadrature operation is desired, irrespective of whether the oversampling rate of the sequence is divisible by four or only divisible by two. This ability is obtained by controlling whether the quadrature mixer clocks coincidentally with the in-phase mixer, or clocks a half clock cycle out of phase relative to the in-phase mixer. Several advantages attend the contemplated circuit arrangement and method of operation. Example advantages include the improved matching that comes from operating both mixers with the identical waveform sample values, and the improved flexibility in optimizing the harmonic rejection and/or interference-related operation of the mixers over a broader range of frequencies of interest, which flows from having a larger set of usable OSRs.

Abstract: Aspects of a method and system for adaptive tone cancellation for mitigating the effects of interference are provided. In this regard, an Ethernet PHY may receive one or more signals via a corresponding one or more physical channels and generate one or more estimate signals, each of which approximates interference present in a corresponding one of the received signals. The Ethernet PHY may subtract each one of the estimate signals from a corresponding one of the received signals. The subtracting may occur at the input of one or more slicers in the Ethernet PHY. The received signals may be processed via one or more equalizers in the Ethernet PHY. A decision output of a slicer in the Ethernet PHY may be subtracted from one of the the one or more received signals, and a signal resulting from the subtraction may be utilized to generate the one or more estimate signals.

Abstract: An algorithm to detect single path channel conditions and reduce the span (number of taps) of the equalizer in order to mitigate the performance degradation caused by noisy equalizer taps is disclosed. The algorithm provides two novel components comprising single path scenario detection and single path scenario processing or (equalizer shortening). A single path scenario is detected when the energy concentrated in a single channel impulse response tap divided by the total energy of the taps exceeds a predetermined threshold. When a single path scenario is detected, only the equalizer taps within a variable window around the equalizer tap having concentrated energy are used to filter the received signal.

Abstract: A delta-sigma analog-to-digital converter (ADC) is disclosed. In one embodiment, the delta-sigma ADC includes a dual mode resonator and a plurality of switches. The delta-sigma ADC is configured to operate in a real modulation mode or a complex modulation mode based on settings of the plurality of switches.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: An adaptive equalizer. Implementations of adaptive equalizers may include implementations of 8-QAM adaptive equalizers that may include a signal filter, an adaptive processor coupled to the signal filter and a slicer coupled to the signal filter and the adaptive processor. The slicer may be configured to utilize a plurality of desired signals corresponding to an 8-QAM signal constellation having four quadrants, four levels disposed along the I-axis, and three levels disposed along the Q-axis. The slicer may also be configured to output an error signal by receiving an equalized output signal, processing the equalized output signal by correlating the equalized output signal with a decision region within one of the four quadrants, selecting one of a plurality of desired signals corresponding to the decision region, and calculating the error signal using the desired signal and the equalized output signal.

Abstract: Systems and methods are described for the implementation of a full band cable receiver by using a combination of tuners (e.g., ultra-low power Tuners) and Analog-to-Digital Converters (ADCs) to attain the goal of digitization with reduced power and/or cost. The full-band capture cable receiver can overcome the constraints of conventional cable receiver systems and deliver multiple channels, thereby allowing operators to provide consumers with an increased number of services.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: An I/Q imbalance compensation block of a RF receiver for compensating an imbalance between an in-phase component and a quadrature component of an RF signal is disclosed. The compensation block includes a conjugation block; an adaptive finite impulse response (FIR) filter; and an adder. The filter use filter coefficients iteratively updated at least partly in response to a compensated digital signal. The filter can have a complex number for at least one, but not all of filter taps, and real numbers for other filter taps. The filter can be provided with adaptation step sizes different from filter tap to filter tap. The filter can also be provided with an adaptation step size(s) varying over time. The filter can also be provided with an adaptation step size(s) divided by the square norm of the compensated signal.

Abstract: An embodiment of the invention pertains to demodulating a data communication into a sequence of symbols. In this embodiment, a first filter generates a first convolution between a first plurality of coefficients and the data communication. The data communication is a distortion of a first sequence of symbols selected from a plurality of symbols in a constellation. A first error circuit maps the first convolution to a second sequence of symbols. An adaption circuit adjusts the first coefficients until a convergence at a last one of the symbols in the second sequence. A second filter generates a second convolution between a second plurality of coefficients and the data communication. The second coefficients are initialized to the first coefficients from the adaption circuit. A second error circuit maps the second convolution to a third sequence of symbols.