Abstract: A sync detector includes a correlation computing unit configured to receive signal values corresponding to respective sample points and to compute auto-correlation of the received signal values between sample points of interest and sample points that are situated at a distance equal to a constant number of sample points from the sample points of interest, a correlation value synthesizing unit configured to receive auto-correlation values corresponding to respective sample points obtained by the correlation computing unit and to synthesize the auto-correlation values with respect to at least two sample points among sample points that are spaced apart by the constant number of sample points thereby to compute a synthesized correlation value, and a peak-point detecting unit configured to detect a position of a sample point corresponding to a largest synthesized correlation value among synthesized correlation values corresponding to respective sample points obtained by the correlation value synthesizing unit.

Abstract: A method and system for reducing power consumption of OFDM (Orthogonal Frequency Division Multiplexing) signal synchronization circuit comprises a sync setting, a sync controller, a sync pipeline and a data corrector. The sync setting dynamically changes correlation data sample rate based on synchronization statuses and results. The sync controller controls and schedules frame and symbol synchronizations, and turns on and off the sync pipeline based on synchronization activities. The sync pipeline integrates frame and symbol synchronization operations, synchronizes receiving signal with scalable synchronization window, synchronization sequence length, synchronization delay and variable data sample rate. Data corrector adjusts input data with coarse timing and fine frequency offsets estimated in sync pipeline, and generates corrected output data for further processing. By using the above techniques, the power consumption of signal synchronization circuit is reduced.

Abstract: An optical communication device using a digital coherent reception system includes a phase detector configured to generate, based on a signal obtained in a course of digital signal processing, a phase signal indicating a displacement of a sampling of a reception signal, a clock switch-determiner configured to switch from an reference clock to a clock of transferred data when a value of an amplitude of the phase signal exceeds a given threshold value, and a selector configured to synchronize the sampling of the reception signal and an internal clock of the digital signal processing with the reference clock at start time or signal loss time, and synchronize the sampling of the reception signal and the internal clock with the line clock of the reception signal except for the start time and the signal loss time.

Abstract: Systems and methods are provided to permit indirect measurements of sample time errors using multiphase interpolator clocks generated from a local reference clock in clock recovery blocks of high speed data receivers. The multiphase interpolator clocks are adjusted to have substantially evenly spaced phase offsets within a data period of the local reference clock. A small frequency offset between the transmitter clock and the local reference clock causes transition edges of received data to drift slowly across the interpolated clocks. Differences in phase offsets between the interpolated clocks may be determined with high resolution by counting the number of data transitions occurring between pairs of interpolated clocks over a long period of time. Phase offsets are adjusted to make the data transition counts substantially the same for the interpolated clocks.

Abstract: A source communication device includes a source network clock to control timing of communicating with other devices in a network, a source streaming clock associated with processing of audio or video data, a time stamp generator to generate a time stamp that includes a source network clock value and a source streaming clock value, and a time stamp insertion mechanism that incorporates the time stamp into a data unit that is to be transmitted to one of the other devices in the network. A sink communication device includes a sink network clock synchronized with the source network clock, a sink streaming clock associated with processing of audio or video data, and a sink time stamp mechanism to compare a sink streaming clock value with the source streaming clock value, and adjust the sink streaming clock based on the comparison.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

Abstract: A Time Division Duplex (TDD) communication apparatus and an operation method thereof can provide operation clock signals in the transmission and reception of the TDD communication apparatus using a Clock Recovery & Data Retiming (CDR) circuit, thereby stabilizing an operation without any crystal oscillator and reducing the power consumption. In a transmission time interval, a transmitting frame is processed using a clock signal of a reference frequency generated from the CDR circuit. In a reception time interval, a receiving frame is processed using a clock signal recovered from the receiving frame by the CDR circuit.

Abstract: A timing recovery system that provides a timing estimate between a transmitter clock and a receiver clock. The system includes a down-converter that converts a received intermediate frequency signal in the receiver and down-converts, using Fs/4 down-conversion, the received signal into baseband in-phase and quadrature phase signals. The baseband in-phase and quadrature phase signals are sent to a direct down-converter that frequency shifts the in-phase and quadrature phase. The frequency-shifted in-phase and quadrature phase baseband signals are then low-pass filtered in order to isolate the frequency components of interest, reduce noise, and remove zeros that are artifacts of the Fs/4 down-conversion. The signals are sent to a square-law non-linearity circuit that provides squaring non-linearity to generate non-linear in-phase and quadrature phase signals. The non-linear in-phase and quadrature phase signals are sent to a single-pole, low-pass post-filter circuit that generates the timing estimate.

Abstract: A method for providing timing recovery from a received digital data stream where the digital data stream is a series of consecutive data samples. The method separates the data stream into a series of consecutive observation periods where each observation period includes the same number of consecutive data samples. The method also includes identifying a series of consecutive timing recovery data samples in each observation period where the timing recovery data samples are used for timing recovery and other data samples in the observation period are not used for timing recovery, and where the number of data samples used for timing recovery in each observation period is less than the number of data samples that are not used for timing recovery in the observation period. The method then uses the timing recovery data samples for timing recovery in each observation period.

Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: An intermittent operative communication apparatus can send data, received from a source communication device, to any receiver communication device at a predetermined interval and wait for receiving data at the predetermined interval. The communication apparatus has a selector for selecting one or multiple receiver communication devices as a reference communication device that gives a reference timing at which the communication apparatus waits for receiving data, and a timing controller for setting a timing, at which the communication apparatus waits for receiving data, to a timing according to operation of any reference communication device.

Abstract: A code controller configures a code state at a substantially constant and low storage volume, and at a substantially constant computational processing amount, regardless of which state position a desired code state is present in within the state area of the code states. In one embodiment, a state processor detects the position of a desired code state based on an inputted code phase amount. Based on the detection, state processor performs processing for jumping the code state a predetermined interval, and obtains a specific code state near the code state. The state processor selects the appropriate process from among a process for delaying the code state one state at a time from the obtained code state and a process for transiting the code state one state at a time in the direction opposite the delay direction, transits the code state, and obtains the desired code state.

Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

Abstract: Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.

Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

Abstract: Disclosed is a technique related to a method and apparatus for generating a preamble and a data frame for wireless communication, and to a synchronization estimation method using the preamble. According to the technique, a method for generating a frame for wireless communication is disclosed, wherein the method comprises: a step of generating a modified sequence using a first base sequence for synchronization estimation; and a step of allocating the first base sequence and the modified sequence to the frequency domain of a first timeslot to generate a preamble. The modified sequence includes a complex conjugated sequence of the first base sequence or a sequence having a code different from that of the first base sequence.

Abstract: A system and method are provided for synchronizing a programmable timer time base and external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions include input capture, output compare, quadrature decoding, pulse measurement, frequency measurement, and pulse width modulation (PWM) functions. In one aspect, accepting the external time signal at the external interface includes detecting a packet with a time value. In another aspect, the method uses the channel to detect an event at a channel external interface, and compares the channel time base counter value with an expected value to modify the synchronized time base.

Abstract: One embodiment of the present invention relates to a method and apparatus for performing both phase modulation (PM) and amplitude modulation (AM) downstream of a controlled oscillator (e.g., by providing a baseband signal having no phase modulation to a controlled oscillator and performing phase modulation on a high frequency RF signal output from the oscillator), wherein the amplitude modulation is synchronized with the phase modulation. In one particular embodiment, the method and apparatus synchronize modulation of AM and PM signal paths in a manner that provides a polar modulated signal having an amplitude of zero at a symbol boundary (e.g., a transition between different symbols) having a phase of zero (e.g., a phase that crosses through a zero crossing point).

Abstract: A synchronization sequence (preamble) that is known to the receiver forms as an integral part of packet-based digital communication systems. The first operation in such digital communication systems is the detection of the beginning of a valid signal (packet). A system, apparatus, and method for a scheme to robustly detect the preamble are provided having a hierarchical cross-correlator in combination with a second stage delayed auto-correlator using the output of the cross-correlator as an input to the second stage correlator.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: In some embodiments, SSC (e.g., discrete SSC) profiles with intentional and controlled gaps may be used to mitigate interference for platform radios. Targeted frequency gaps are placed in spectrum of spread clocks and clock-derived signals where they may otherwise result in problematic RFI to a platform radio.

Abstract: In at least some embodiments, a receiver includes channel estimation logic configured to a process a long training field symbol having a doubled cyclic prefix. The channel estimation logic is configured to vary an amount of the doubled cyclic prefix used for channel estimation. Further, in some embodiments, a wireless communication device includes logic to enable communications based on at least two long training field symbols having a doubled cyclic prefix as part of a synchronization header. Further, in some embodiments, a method includes receiving a long training field symbol having a synchronization header with a doubled cyclic prefix and varying an amount of the doubled cyclic prefix used for channel estimation.

Abstract: The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.

Abstract: Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

Abstract: A system and method for detecting electrical idle in a receiver is disclosed herein. A receiver includes a differential receiver, an analog idle detector, and a first filter. The differential receiver receives a variable rate differential signal. The analog idle detector is coupled to the differential receiver. The analog idle detector provides a first idle signal that erroneously identifies a differential signal electrical idle state. The first filter is coupled to the analog idle detector. The first filter processes the first idle signal and generates a second idle signal lacking the idle state errors of the first idle signal. The first filter provides the second idle signal to receiver control logic that controls signal reception.

Abstract: The present invention discloses a method for single-wire transmission without clock synchronization, comprising: providing three states; defining a spacing bit by a first state of the three states; and defining data signals, a start signal and an end signal by combinations of the second and third states of the three states.

Abstract: In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation.

Abstract: A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit 11 for detecting whether D1?D2 or D1?D3, assuming that logical values of an input data signal DATAIN sampled at timings t1, t2, and t3 (t2<t1<t3) of edges of clock signals CLK0 and CLK1 are D1, D2, and D3, respectively; and a clock generation circuit 14 for changing phases of the clock signals CLK0 and CLK1 based on detection results from the detection circuit 11, so that timings at which the logical values of the input data signal DATAIN change correspond to the timings t2 and t3.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: The present invention provides telecommunications transport methods and systems for the transparent mapping/demapping of client data signals without the insertion/deletion of idle characters for client data signal rate adaptation. These methods and systems include mapping an incoming client data signal to and demapping an outgoing client data signal from a transport frame comprising: a first segment that is dedicated to client data; a second segment that is dedicated to fixed stuff, wherein the fixed stuff comprises, for example, network management information; a third segment that is dedicated to justification data for supporting a client data signal rate adaptation function; and a fourth segment that is dedicated to justification control information for indicating whether the third segment is used for client data or fixed stuff, wherein the justification control information is redundant for error protection purposes.

Abstract: The invention is directed to a method and system for providing centralized automated synchronization clock reconfiguration in packet switched telecommunications networks having network nodes that do not implement Synchronization Status Messaging (SSM) internally. This is especially useful when integrating TDM networks with packet switching network elements having T1 and E1 interfaces.

Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Abstract: In a multiple-input, multiple-output system, the wireless node's receive chain demodulation function is enhanced to include phase tracking. Instead of performing phase tracking during the data symbols which is cumbersome for very high throughput wireless networks, the VHT Long Training Fields (LTFs) embedded in the preamble of a frame are used for phase tracking. Single stream pilot tones are added during the transmission of VHT-LTFs. This is exploited on the receive side to be able to estimate the channel using the pilot tones in the first set of the Long Training Fields. Second set of the Long Training Fields are then used to estimate the phase of the pilot tones using the estimated channel. The phase estimation so obtained is continuously applied to other received data tones throughout the VHT-LTFs of the data symbols.

Abstract: Processing the synchronization of an inband modem to detect sample slip conditions is disclosed. Decision logic reliably detects the sample slip condition while minimizing the number of false alarms.

Abstract: A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data.

Abstract: A method of operating a communication system comprises establishing a wireless device release time interval for a wireless device release timer at an access node upon establishing an initial network connection between a wireless device and the access node. An initial synchronization process is performed between the wireless device and the access node. The method continues with the access node sending an unsolicited synchronization message to the wireless device and starting the wireless device release timer. A second synchronization process is performed and upon successful completion of the second synchronization process, a success status synchronization response message is sent by the access node to the wireless device. The access node receives a synchronization confirmation message from the wireless device that comprises an identifier corresponding to the identity of the wireless device and upon receiving the confirmation message, the access node cancels the wireless device release timer.

Abstract: A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated NICAM audio samples. A phase differential calculator may be included that compares phase information at different resolutions.

Abstract: The present invention provides methods and systems for allowing a receiver in a (wireless) communication system to synchronize its timing and frequency subsystems in accordance with a received signal. In accordance with one aspect, a method is provided in which a relative time of arrival of sync values provided in a received signal are determined and used to align the receiver's reference signal(s) accordingly. Other aspects of the invention will become apparent from the detailed description of exemplary embodiments that follows.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.

Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.

Abstract: A radio communication apparatus connected to a device including a digital signal processing unit generating a clock signal, the apparatus includes an acquisition unit acquiring frequency information concerning the clock signal from the digital signal processing unit, a first measurement unit measuring a signal power in a first frequency band, a comparison unit comparing the signal power with a threshold, a first selection unit selecting, from the first frequency band, a second frequency band necessary for data communication, a bandwidth of the first frequency band whose signal power is lower than the threshold being more than a bandwidth of the second frequency band, a second selection unit selecting an optimum communication scheme from a plurality of communication schemes of the data communication according to the frequency information, and a communication unit using the optimum communication scheme to perform the data communication in the second frequency band.

Abstract: A synchronous pattern detection section checks coincidence between a predetermined reference synchronous pattern and a bit pattern included in a data stream. Each time a bit pattern which coincides with the reference synchronous pattern is detected, the synchronous pattern detection section extracts a frame length of a data frame corresponding to the bit pattern which is detected, and stores the extracted frame length in a storage section. Each time a bit pattern which coincides with the reference synchronous pattern is detected in the synchronous pattern detection section, a synchronization determination section determines whether or not the bit pattern detected by the synchronous pattern detection section is a correct synchronous pattern, based on a plurality of frame lengths stored in the storage section and a bit length of a data stream which is obtained after detection of the bit pattern. With this structure, a synchronous pattern included in the data stream can be detected with higher precision.

Abstract: This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.

Abstract: A method for implementing variable symbol rate, presetting counters M and N, and M=1, N=0, f being the preset output symbol rate, fs being the frequency of input clock, the method comprises: triggering to judge whether N×f is greater than M×fs at the rising edge of the input clock, if it is, letting the counter M add 1 and outputting a clock pulse; else further judging whether the value of the counter N is equal to fs?1; when N=fs?1, letting the counter N return to 0, and waiting for the next rising edge of the input clock; when N?fs?1, waiting for the next rising edge of the input clock after letting the counter N add 1; letting the output clock pulse be the system clock, controlling the data to be output to set the symbol rate output.

Abstract: A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.