Abstract: In accordance with an embodiment, the vectoring controller is configured to iterate through successive crosstalk acquisition cycles and, within respective ones of the crosstalk acquisition cycles, to configure sequences of crosstalk probing symbols for transmission over the respective communication lines, to receive sequences of error samples as successively measured by respective receivers coupled to the respective communication lines while the sequences of crosstalk probing symbols are being transmitted, and to determine crosstalk estimates between the respective communication lines based on the sequences of error samples. The vectoring controller is further configured to randomize the successive sequences of crosstalk probing symbols used during the successive crosstalk acquisition cycles, and to iteratively configure the vectoring processor based on the successive crosstalk estimates.

Abstract: The invention relates to decoding utilizing image data. The image data can be received from a source. A processor can process the image data for decoding. Processing for decoding can be responsive to determined information. The format of a frame of image data may be recognized. The recognizing may include determining the source of the frame of image data. The recognizing may include determining a parameter associated with the frame of image data.

Abstract: Various aspects provide for modifying a data stream for rate adaptation. A clock component receives a data stream at a first clock rate. In an aspect, a rate adaptation component inserts a first identification codeword into a particular location in the data stream based on a set of encoding rules in response to a determination that the first clock rate is lower than a second clock rate associated with a device configured for receiving a rate-adapted version of the data stream. In another aspect, the rate adaptation component removes a predefined codeword from the data stream and transforms another predefined codeword in the data stream into a second identification codeword in response to a determination that the first clock rate is greater than the second clock rate.

Abstract: Methods and systems for augmenting a source message by suitably-chosen bits and/or sequences of bits for the purpose of enhancing decoding or synchronization performance. Properties of the source message can be used to select and optimize synchronization sequences, including their length and placement within the source message. Various message attributes, such as message or segment weight, symbol counts, and others, including their combinations, may be encoded into the synchronization sequence to further improve decoding performance in the presence of errors. These methods and systems can be employed for standalone source decoding of noisy bit streams, as well as iterative joint source-channel decoding. They may further be combined with other methods whether or not known in the art, such as CRC and forward error correction, to achieve the desired performance complexity trade-off.

Abstract: Instant discloser is a method to transmit multiple data-streams of varying capacity data using Virtual Concatenation (VCAT) over Synchronous Digital Hierarchy (SDH) network, comprising acts of determining number of data bytes to be requested for each Virtual Concatenation Group (VCG) in a row-time of the aggregated bandwidth and storing it in a VCG request configuration memory, reading the requested number of data bytes from each data-stream in order in to a Row Buffer for each row time of an SDH frame, reading data stored in the Row Buffer from memory address determined by one or more connection memory wherein the connection memory is programmed to carry out sequencing of bytes of the Row Buffer based on the VCAT numbering, and inserting path overhead (POH) and pointer information in to the read data streams in previous step to transmit multiple data-streams of varying capacity data using VCAT over SDH network.

Abstract: A system including a demodulation module, a metric generation module, and a preamble detection module. The demodulation module is configured to generate demodulated signals based on demodulating, in accordance with a differential demodulation scheme, signals received from a base station. The signals received from the base station include a plurality of symbols. The demodulated signals comprise a plurality of real parts each having a corresponding magnitude. The metric generation module is configured to generate a plurality of metrics for the plurality of symbols based on the corresponding magnitudes of the plurality of real parts of the demodulated signals. The preamble detection module is configured to detect, based on the plurality of metrics, whether the plurality of symbols in the signals received from the base station includes a preamble symbol.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.

Abstract: Apparatus and method for embedding data in initial content having synchronized video and audio, the method comprising defining at least one content segment in the initial content, and altering the video and audio synchronization in the at least one segment in accordance with the data to be embedded, wherein the altered content segment is viewable on a viewing device and the synchronization alteration is imperceptible to a casual viewer. Related apparatus and methods are also described.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.

Abstract: A method and apparatus for detecting an overlap of an E-DCH transmission or retransmission in TTIs that overlap with an assigned uplink compressed mode gap is disclosed. More specifically, detecting an overlap of an E-DCH transmission or retransmission in TTIs that overlap with an uplink compressed mode gap assigned by a Node B when a WTRU is configured with a 2 ms TTI is disclosed. After detecting the overlap of the E-DCH transmission or retransmission and the uplink compressed mode gap, the E-DCH transmission or retransmission is paused.

Abstract: A medical sensor system comprises a gateway comprising a wideband receiver and a narrow band transmitter, the each gateway configured to receive a wideband positioning frame using the wideband receiver from one or more wearable sensors and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the sensors to establish timing for transmission of the positioning frame; and at least one wearable sensor comprising a wideband transmitter and a narrow band receiver, the sensor configured to transmit a sensor data frame to the gateway using the wideband transmitter and to receive an acknowledgement frame from the gateway using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital broadcasting. The receiver may be enabled to dynamically vary spacing between two or more pilots and/or the size of one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between two or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: A positioning system comprises a plurality of controllers, each controller comprising a wideband receiver and a narrow band transmitter, the each controller configured to receive a wideband positioning frame using the wideband receiver from one or more devices and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the devices to establish timing for transmission of the positioning frame; and at least one device comprising a wideband transmitter and a narrow band receiver, the device configured to transmit a positioning frame to the plurality of controllers using the wideband transmitter and to receive an acknowledgement frame from one or more controllers using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.

Abstract: Method and apparatus to synchronize packet rate for audio information are described.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: A method of recovering data in a line signal which is predicted to be subjected to repetitive noise impulses, the line signal comprising a series of data frames, the method comprising the steps of: predicting a group comprising one or more frames in said line signal which are expected to be corrupted by a noise signal; blanking said group of one or more frames which are predicted to be corrupted; determining the preceding and succeeding frames adjacent to said group; and including in each said group of one or more frames one or more parity blocks wherein if said noise signal deviates from its predicted timing interval or duration and corrupts the data carried in one or more of said frames adjacent to said group, the corrupted data is recovered using one or more of said parity blocks of said group of blanked frames and the other one of said adjacent frames.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: A system including a magnitude measuring module, an energy normalization module, and a metric generation module. The magnitude measuring module is configured to measure magnitudes of real portions of differentially demodulated signals, wherein the differentially demodulated signals are generated by differential demodulation of signals received from a base station. The energy normalization module is configured to generate a sum of energies of a plurality of subcarriers included in the signals received from the base station. The metric generation module is configured to generate a plurality of metrics for a plurality of symbols included in the signals received from the base station. The metric generation module is further configured to detect, based on the plurality of metrics, a preamble symbol included in the signals received from the base station.

Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

Abstract: A synchronization method and related apparatus of an OFDM digital communication system are disclosed for determining a position of a synchronization byte in a received signal. The method includes extracting a transmission parameter signal (TPS) from the received signal, determining a symbol number and a frame number corresponding to a symbol according to the TPS, and determining the position of the synchronization byte according to the frame number and the symbol number.

Abstract: The present invention provides a unique manner of identifying the Frame boundaries in multiple identical/non-identical Synchronization Channels (SCHs) in different sub-frames via a new sub frame position difference method. The method implements the differences between the different sub-frames carried by the SCH. The sub frame identity, and hence the frame boundary, can be identified by calculating the difference between the positions, based on time or number of slots/sub-frames or any data packets, of the two subsequent slots/sub-frames or any identical data packets.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the associated receiving part to its clock.

Abstract: A system for implementing an orthogonal frequency division multiplexing scheme and providing an improved range extension. The system includes a transmitter for transmitting data to a receiver. The transmitter includes a symbol mapper for generating a symbol for each of a plurality of subcarriers and a spreading module for spreading out the symbol on each of the plurality of subcarriers by using a direct sequence spread spectrum. The symbol on each of the plurality of subcarriers is spread by multiplying the symbol by predefined length sequences. The receiver includes a de-spreader module for de-spreading the symbols on each of the plurality of subcarriers. The de-spreader module includes a simply correlator receiver for obtaining maximum detection. The correlator produces an output sequence of a same length as an input sequence and the de-spreader module uses a point of maximum correlation on the output sequence to obtain a recovered symbol.

Abstract: A method and apparatus for detecting an overlap of an E-DCH transmission or retransmission in TTIs that overlap with an assigned uplink compressed mode gap is disclosed. More specifically, detecting an overlap of an E-DCH transmission or retransmission in TTIs that overlap with an uplink compressed mode gap assigned by a Node B when a WTRU is configured with a 2 ms TTI is disclosed. After detecting the overlap of the E-DCH transmission or retransmission and the uplink compressed mode gap, the E-DCH transmission or retransmission is paused.

Abstract: A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) while another signal is delayed by a delay unit (310). The signal multiplier (312) multiplies the received signal (316) by a delayed signal (318). An integrator (314) integrates an output signal (322) over a designated period of time. An adding module (306) sums an output signal (324) from the integrator (314). An acquiring module (308) compares an summing-up output (326) from the adding module (306) with a predetermined threshold value to detect the existence of a transmitting-standard preamble.

Abstract: A system includes an input, a differential demodulation module, a magnitude measuring module, a summing module, and a metric generator module. The input receives input signals that include s sets of modulated sub-carriers carrying symbols, where s is an integer greater than or equal to 1. The differential demodulation module generates differentially demodulated signals based on the input signals. The magnitude measuring module measures magnitudes of real portions of the differentially demodulated signals. The summing module generates s sums, wherein each of the s sums is a sum of the magnitudes generated based on a respective one of the s sets. The metric generator module generates metrics for the symbols based on the s sums.

Abstract: A system including a differential demodulation module that receives modulated signals from R antennas and that differentially demodulates the modulated signals to generate differentially demodulated signals, where R is an integer greater than or equal to 1. A summing module sums the differentially demodulated signals to generate a combined signal. A correlation module correlates the combined signal with derived preamble sequences and generates correlation values based on the correlation. The derived preamble sequences are derived from preamble sequences. Each bit of one of the derived preamble sequences has a first state when a corresponding bit and a bit adjacent to the corresponding bit in a corresponding one of the preamble sequences have opposite states. Each bit has a second state when the corresponding bit and the bit adjacent to the corresponding bit have the same state.

Abstract: A clock synchronization circuit includes a clock generation circuit generating a sampling clock for sampling a received signal from an output of a local oscillator, a phase error detection circuit finding a phase error between sampling timing of the sampling clock and ideal sampling timing, and a timing correction circuit finding a correction quantity to correct a frequency error between a frequency of the sampling clock and a frequency of the ideal sampling timing and the phase error every sampling timing of the sampling clock, and outputting a sampling value interpolated according to the found correction quantity.

Abstract: A scheme for detecting a symbol timing (synchronization) of an Orthogonal Frequency Division Multiplexing (OFDM) system in which a transmitting end inserts a Cyclic Prefix (CP) and/or a Cyclic Suffix (CS) in an OFDM symbol for transmission, and a receiving end uses a new timing metric to detect a timing (synchronization) of the OFDM symbol based on a maximum value of the timing metric, whereby when applying the method for detecting the symbol timing of the OFDM system according to the present invention, the symbol timing can be obtained more precisely, to thusly enable stabilizing of performances of the OFDM system.

Abstract: Methods and systems provide approaches to start code emulation prevention at a granularity higher than the bit level. By operating at a level other than the bit level, processing capability requirements on both the encoder and decoder side can be reduced. In accordance with one or more embodiments, a start code emulation prevention method looks for data patterns relative to fixed-size data portions larger than single bits. When a particular pattern is found, start code emulation prevention data is inserted to prevent start code emulation. The inserted data is larger than a single bit and, in some embodiments, comprises a byte. When a decoder decodes data that has had start code emulation prevention data inserted, it can easily identify legitimate start codes and then can remove the start code emulation prevention data to provide the original data that was protected.

Abstract: A MODEM device includes a detector configured to detect a synchronization signal transmitted from a source MODEM in a resynchronization process of a primary channel and a timer configured to count up starting from a beginning of a detection of the synchronization signal, and send information to forcibly move into a receiving mode for receiving image data when a time period from the beginning to a completion of the detection of the synchronization signal exceeds a predetermined time period.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: Provided are a method for measuring characteristics of a path between nodes by using active testing packets based on priority, i.e., an inter-node path characteristic measuring method, which can measure and provide characteristics of a generated node, when an inter-node data transmission path is generated based on Multi-Protocol Label Switching (MPLS) to provide a path with satisfactory transmission delay, jitter and packet loss that are required by a user, and to provide a computer-readable recording medium for recording a program that implement the method. The method includes the steps of: a) synchronizing system time of the nodes with a global standard time; b) forming each testing packet; c) registering frame sequence and the global standard time during transmission; and d) calculating transmission delay time, jitter and packet loss by using time stamp and packet sequence information of a frame received by the destination node and transmitting the result to the management system.

Abstract: The techniques described herein allow a more efficient transmuxing operation for transferring data from a synchronous domain (e.g., SONET) to a plesiochronous (e.g., PDH) domain as compared to the prior art, in which extraction of data streams, jitter filtering and stuff bit generation are processed separately. The techniques described herein include extraction of data from the plesiochronous data stream without complete extraction of the underlying native data stream. Filtering is performed based on synchronous timing, which results in a simpler filter design.

Abstract: A synchronization extraction apparatus for a communication system and a method thereof are disclosed. A frame synchronization is obtained in a manner that the sum of an input signal and a delay signal is obtained without obtaining a simple correlation value between the input signal and the delay signal, and then a correlation value between a summed signal and the delay signal is obtained. The synchronization extraction apparatus and method can reduce the implementation complexity and power consumption in obtaining the frame synchronization, and thus increase the battery cycle of a terminal provided with the synchronization extraction apparatus or method.

Abstract: A method and system for transmitting signals between communication nodes is presented. The method includes generating a first waveform that includes a shaped portion; generating a second waveform that includes a shaped portion; and combining the first and second waveforms including overlapping the shaped portion of the first waveform with the shaped portion of the second waveform and adding the overlapped portions of the waveforms. The method includes generating a signal including the combined first and second waveforms. At least one of the first and second waveforms includes a characteristic signature configured for synchronizing with the signal.

Abstract: A method and system for efficiently delivering messages from a service provider to individual receiving devices in a unidirectional, multi-channel communications system that provides parallel distribution of information from the service provider to the receiving devices. The messages are transferred from the service provider to the receiving device only on an agreed-upon channel at an agreed-upon time, wherein each message is tagged with an address corresponding to the receiving device by the service provider and then transmitted by the service provider to the receiving device on the agreed-upon channel with the receiving device filtering the agreed-upon channel to detect the address and decode its messages. The agreed-upon channel and the agreed-upon time of message transfers are coordinated between the service provider and the receiving device prior to transferring the message from the service provider to the receiving device.

Abstract: The present invention relates to a communication system and method for transmitting sync flags and pilot symbols during sync symbol periods. Example embodiments provide a method for sharing sync symbols to communicate flag sequences and pilot sequences during a sequence of sync symbol periods. The method includes modulating the pilot sequence by multiplying a pilot code by each value of the pilot sequence, and modulating the flag sequence by multiplying a flag code by each value of the flag sequence. The pilot and flag codes are mutually orthogonal to each other and each includes at least two non-zero values. The method further includes generating a resulting sync symbol sequence based on the modulated pilot sequence and modulated flag sequence, and sending the resulting sync symbol sequence during the sync symbol period.

Abstract: A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

Abstract: A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

Abstract: This invention relates to signal processing in telecommunications, particularly but not exclusively for use in wireless TDMA systems. In particular, the invention concerns methods for use in communication systems making use of pilot symbols. The invention provides a method of placing pilot symbols in a data stream for telecommunication systems, wherein the pilot symbols are spaced in time using a range of different intervals between symbols. The intervals between the pilot symbols are substantially fractal in nature, the distribution of pilot symbols involving repetitions of irregular groupings of pilot symbols in the data stream. Preferably, the irregular groupings of pilot symbols are irregularly spaced in the data stream. The invention also provides a method and means for acquiring the time and frequency offset of a packet of data by using pilot symbols distributed within the packet as defined above.

Abstract: An information processing apparatus and method, a recording medium, and a program for removing jitter and reducing the delay of the information processing system. A substantial error is produced between accumulated value of intervals of reception time of the packets and accumulated value of time stamps of these packets. For each number of transport stream packets on which this substantial error provides one clock, a time equivalent to one clock is added to the subsequent time stamps of the transport stream packets or this time is subtracted therefrom to adjust time stamp, thereby correcting the deviation in time from reception time of the transport stream packets.

Abstract: The present invention provides an audio data sync format detecting circuit that can minimize both the hardware configuration software processing, and furthermore, has a large flexibility with respect to unknown formats. Audio data is written in sequence into a data register, where the audio data are units having a predetermined number of bits. Samples of the format that is the object of detection are written in sequence into a register. A comparator compares the data in the sample register and the data in the data register. A control circuit receives hit signals and outputs an interrupt signal to the controller, and the controller writes in sequence samples of the format that is the object of detection into the register each time an interrupt signal is received. When hit signal is continuously output a predetermined number of times, a match detection circuit outputs a format match signal.

Abstract: An apparatus for compensating nonlinearly distorted multicarrier signals, a multicarrier signal receiver using the same, and a method therefor are provided, where the apparatus for compensating multicarrier signals and the multicarrier signal receiver using the apparatus extract parameter information on the HPA mode from the received signal so that nonlinear distortion of the received multicarrier signal is compensated for even though an accurate transfer function of a high power amplifier (HPA) is not known and side information or a special training signal is not transmitted when a signal is transmitted, such that nonlinearly distorted multicarrier signals such as OFDM signals transmitted by an HPA having a variety of transfer functions can be adaptively compensated and therefore a demodulated signal with an improved symbol error rate (SER) can be obtained.