Abstract: Various embodiments are described to provide for the transmission and reception of data in an improved manner. Data transmission is improved by including in a transmitter a null generator (110) to generate an output data symbol sequence that exhibits nulls in the frequency domain at particular frequencies that an input data symbol sequence does not. A pilot inserter (120) then adds a pilot symbol sequence to this output data symbol sequence to create a combined symbol sequence. Since the pilot symbol sequence exhibits pilot signals corresponding to the nulls of the output data symbol sequence in the frequency domain, the combined symbol sequence exhibits pilots that are orthogonal to the data in the frequency domain.

Abstract: A DSRC communication technology that prevents unique word detection errors even when the frame changes in data reception and the timing of the unique word detection window and the timing of the received data do not match, and that adjusts the data transmission timing in a flexible fashion when the slot timing deviates from the frame timing. In this technology, bit counter 111 generates the frame timing from the frame synchronization signal, and bit counter 112 generates the sot timing in response to the slot synchronization signal. The unique word detection window is generated from the frame timing and the received data operation timing and the data reception timing are generated from the slot timing. In addition, the data transmission timing and the transmission data operation timing are generated based on one of the frame timing and the slot timing chosen in selector 123.

Abstract: A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to communicate a change in a bit pattern of the signal. A synchronization pattern is generated using knowledge of phase rotation direction due to two consecutive bits in a synchronization key. The signal is compared with the synchronization pattern. It is determined whether the comparison of the signal and the synchronization pattern indicate a correlation between the signal and the synchronization pattern.

Abstract: In a device for processing data signals, a storing part stores an input signal and the data signals included in the input signal are extracted from the storing part and the data signals are output at a desired output speed. Then, the data signal is output based on storage information of the input signal.

Abstract: A method for transmitting synchronization information with data, which data corresponds to a sequence of samples representative of a signal, includes detecting the occurrence of two consecutive equivalent samples and inserting a synchronization pattern for the second-occurring sample prior to transmission. At a receiving end, the incoming signal is monitored to detect the presence of the sync pattern and hold the value of the receiver output at the value of the immediately previous received sample. In this manner, the signal is reconstructed without degradation, and byte synchronization information is sent without any bandwidth loss.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The retimers are configured to retime, amplify and retransmit a received data stream without altering the received data rate. Thus, the data rate from the first node is received at the same frequency at the last node, regardless of the number of retimers. In general, the retimer performs rate compensation on a retimer local clock, rather than on the data stream, so the attributes of the clean retimer clock can be applied to the data stream without changing the data rate.

Abstract: In an embodiment, an apparatus includes a storage unit to store data from a data signal. The apparatus also includes control circuitry coupled to the storage unit. The control circuitry is to cause the storage of the data from the data signal into the storage unit at a nominal rate upon determining that the data signal includes a number of errors.

Abstract: A method of transmitting digital signals which are passed via a communication system by means of a retimer between an input and an output, whereby according to the invention the data packet applied to the input is scanned with respect to the individual bits and within the individual bits and preferably at the center and the scanned data level is transmitted immediately to the output.

Abstract: The invention relates to a TDM backplane bus system, in which a Frame Synchronisation signal is developed from an external communication signal, a data clock signal is produced from a free running clock oscillator independent of the FS signal, to select the frequency of the clock signal so that the number of periods within a frame is always at least one more than the number of timeslots required, to synchronise the FS signal to the CLK signal, and supply this synchronised Frame Synchronising signal (FS-S) to the TDM-bus. Further, the exceeding period(s) is identified by introducing a carry bit in the timeslot counters, the carry bit being set each time the counter(s) exceeds the number of timeslots on the TDM bus.

Abstract: A splicing system includes a splicer for seamlessly splicing togther digitally encoded data streams. In a preferred embodiment, the splicer preferably parses successive splice buffers of data stream data for a splice-out point and a splice-in point, closing an initial group of pictures GOP if needed. The preferred splicer further finds a new data stream real-time program clock reference PCR value for aligning new data stream decode/presentation, and aligns the new data stream start time. Concurrently, the splicer preferably uses a frame table to detect overflow and corrects such overflow by adding null packets, thereby delaying portions of data stream data. The splicer also preferably restores data stream encoding by deleting null packets, and thereby accelerating a portion of data stream data. In a further preferred embodiment, the splicer preferably uses a bit-clock schedule offset to delay or accelerate portions of data stream data.

Abstract: A spread-spectrum phase-locked loop clock generator includes a PLL circuit, a modulation generator, a bit stream processor and a multiplexer. The modulation generator outputs a bitstream in response to an input signal and a control signal. The bitstream processor generates bitstream signals. The multiplexer outputs one of the bitstream signals in response to a frequency deviation control signal. The PLL circuit is controlled by the output of the multiplexer.

Abstract: The repetitive structure of a preamble signal is exploited to enhance timing synchronization performance and frame start detection performance under adverse channel conditions. Received values are cross-correlated in time against a known noise-free version of the preamble. The presence of peaks in the cross-correlation output indicates presence of a frame. The peak locations provide symbol timing. Further cross-correlation processing and/or non-linear processing can be used to enhance the signal to noise ratio of the peaks.

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.

Abstract: The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.

Abstract: A transmission method uses multiple kinds of control codes to be exchanged on a serial transmission path between a sender side and a receiver side, and each of the multiple kinds of control codes has bits smaller in number than a predetermined fixed length.

Abstract: An apparatus comprising an analog circuit, a first digital circuit, and a second digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The first digital circuit may be configured to generate (i) one or more data signals, (ii) a first strobe signal, and (iii) a second strobe signal in response to the plurality of samples, the plurality of phases, and a correction signal. The second digital circuit may be configured to generate the correction signal and a width signal in response to (i) the one or more data signals, (ii) the first strobe signal, and (iii) the second strobe signal.

Abstract: An orthogonal frequency division multiplexing (OFDM) transmitter method, consistent with certain embodiments of the present invention arranges OFDM data symbols representing data bits for transmission in a packet. A prescribed pattern of OFDM data symbols are removed (212) and replaced (216) with pilot symbols. The packet is then transmitted (220) to an OFDM receiver that receives the packet (224) and determines a channel correction factor from the pilot pattern. The receiver then estimates a plurality of channel correction factors, one for each of the plurality of OFDM symbols representing data (228) and uses these correction factors to correct the OFDM symbols representing data (232). Arbitrary data are then inserted in place of the pilot symbols (236). The OFDM symbols representing data along with the arbitrary data are then decoded using an error correction decoder that corrects the errors induced by substitution of the pilot symbols for data symbols (240).

Abstract: A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

Abstract: A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

Abstract: An apparatus comprising a parallel arrangement of circuits is described. Each circuit has a data net input. Each circuit has an indication signal net input configured to transport an indication signal having shapes and/or temporal locations different than a data signal on the data net input.

Abstract: Clock information related to a reference clock is distributed from a master network node to a slave network node in an asynchronous packet-based network by embedding the clock information into an additional bit stream and multiplexing the additional bit stream with a primary data stream using an out-of-band channel. Multiplexing the additional bit stream with the primary bit stream using an out-of-band channel may involve selecting yB codes of an xB/yB encoded bit stream to represent bits of the additional bit stream or to balance the running disparity of the xB/yB encoded bit stream. The clock information that is embedded into the additional bit stream is used to generate a clock that is synchronized with a reference clock. In an embodiment, the clock information represents the time difference between a transmitted frame of the additional bit stream and a next edge of the reference clock.

Abstract: A method is provided for transmitting a composite digital audio broadcast signal having an analog portion and a digital portion to mitigate intermittent interruptions in the reception of said digital audio broadcast signal. The method comprises the steps of arranging symbols representative of the digital portion of the digital audio broadcast signal into a plurality of audio frames, producing a plurality of modem frames, each of the modem frames including a group of the audio frames, and adding a frame synchronization signal to each of the modem frames. The modem frames are then transmitted along with the analog portion of the digital audio broadcast signal, with the analog portion being delayed by a time delay corresponding to an integral number of the modem frames. The invention also encompasses radio receivers and transmitters which process signals according to the above methods.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver detects and corrects sampling offsets in the time domain. The OFDM receiver oversamples a training sequence or symbol in a received OFDM signal, correlates the oversampled training sequence with a stored copy of a truncated version of the training sequence, locates a correlation peak, and derives a sampling offset by calculating a difference in magnitude of correlation samples in the vicinity of the correlation peak.

Abstract: In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. A storage circuit stores the lower order group signal outputted from the destuffing circuit. A stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. A variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit.

Abstract: A method and apparatus for multiplexing and demultiplexing multiple serial data streams provide double the data throughput on a single media channel, such as Fibre Channel (EC). A first incoming data stream is routed to a first synchronizer unit, which receives a 0-degree phase signal of a local clock operating at the same basic frequency as that of the incoming data. The first synchronizer unit establishes and maintains synchronization of the first data stream with the 0-degree phase signal. A second incoming data stream is routed to a second synchronizer unit, which receives a 180-degree phase signal of the local clock. The second synchronizer unit establishes and maintains synchronization of the second data stream with the 180-degree phase signal. The synchronizer units maintain synchronization of the respective data streams by applying an elasticity function to the data streams.

Abstract: In all wireless systems, the first operation that must take place at the receiver is the acquisition of the carrier and timing. OFDM systems are particularly sensitive to carrier offsets since these can introduce inter-carrier interference and loss of signal power. An algorithm, termed modulo-sub-carrier (ModSC), which can estimate the local oscillator offset in a fast and efficient manner has been devised. The carrier offset can be brought to within one half the carrier spacing within 1 to 10 OFDM symbols. By inserting a null in the center carrier, carrier acquisition can be easily accomplished by locating this null in the FFT bins at the receiver. The offset of this null from the designed position indicates the local oscillator offset in units of number of sub-carriers. An additional carrier tracking algorithm is used to estimate the offset within one half the inter-carrier spacing. Together, the ModSC and carrier tracking algorithms completely estimate the local oscillator offset.

Abstract: A method of determining an integral portion of a carrier offset &Dgr;fc of an RF signal transmitted from a transmitter at a transmit carrier frequency fct and an apparatus for carrying out the method. The signal consists of at least two data symbols S1 and S2, each having a useful part preceded by a cyclic prefix containing a tail portion of the useful part, such that in the time domain the useful part occupies a symbol interval Ts and the cyclic prefix occupies a guard interval Tg. The carrier offset &Dgr;fc between a receive carrier frequency fcr and the transmit carrier frequency fct is calculated in the form of an integral multiple of the inverse 1/Ts of the symbol interval. The method is especially useful in application to data symbols which are multiplexed by the orthogonal frequency division multiplexing (OFDM) and are constructed from sub-symbols ck belonging to a 2m-ary constellation of complex values equally spaced in phase, such as phase-shift keyed (PSK) constellations, e.g.

Abstract: An apparatus for and method of generating a signal for equalizing propagation delay among parts of a transceiver are disclosed. The parts each have a plurality of channels, and each channel is configured to receive the signal. The apparatus includes a master circuit and a dummy channel circuit. The master circuit is configured to receive and lock to a reference clock signal, and in accordance therewith generate a reference delay signal and an adjusted clock signal. The dummy channel circuit is configured to receive the adjusted clock signal, the reference delay signal and a dummy data signal, and in accordance therewith generate an intermediate data signal, the dummy data signal and one or more control signals. The control signals correspond to a delay between the adjusted clock signal and the intermediate data signal. In this manner a uniform delay may be provided to all parts and channels.

Abstract: An efficient method of accurately estimating delay spread in multi-path transmission applications is based on quantifying the effect of the actual delay spread on the shape of the correlation energy profile between the received signal and the synchronization pattern of the receiver. Depending on the degree of the estimated delay spread, an appropriate demodulation technique is selected for optimizing the receiver performance over a range of channel multi-path conditions. The invention is applicable to digital wireless mobile communication systems, as well as to any device that performs characterization or testing of a transmission system.

Abstract: A direct spread spectrum communication system in accordance with a delayed multiplex mode in which improvement in correlation and improvement in error rate can be perfectly realized in any data length. A data generating section appends addition bits so as to generate an integral multiple of information to be transmitted, from data received from an upper (MAC) layer. The symbol length of a data part is determined from information obtained from the upper layer, and the generating section knows the symbol length of a bit synchronization section, a frame synchronization section and a various information section in the system, which should be originally appended as a packet. Therefore, the number of additional bits are added so that the total number of symbols amounts to an integral multiple of the data to be multiplexed.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: A radio communication device provides extended burst tone detection for a demodulated I and Q input signal. The device includes a first burst detector coupled with the input signal and provides a first detection signal when a FCB tone is detected. A frequency shifter is coupled with the input signal and frequency translates the input signal by a predetermined amount. A second burst detector is coupled with the translated input signal and provides a second detection signal when a FCB tone is detected. A combiner is coupled with the first and second detection signals and indicates FCB tone detection when either of the first and second detection signals indicate FCB tone detection.

Abstract: The present invention relates to a method of inserting sync patterns of different lengths in modulated data, and a recording medium having sync patterns produced by said method. The sector sync and the frame sync pattern to be inserted in modulated data in accordance with the present invention must satisfy the given (d, k) constraints, have distinctive 0's run the modulated channel data can not have, and be as short as it can. In addition, the frame sync pattern is shorter than the sector sync pattern because the frame sync pattern is more frequently inserted than the sector one. Owing to the present sync patterns, the storage capacity reduction of a recording medium due to necessary insertion of sync patterns can be minimized under a given modulation condition.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: The remote unit (113) maintains a count of inserted blank scan lines generated by the remote unit (113) and uses this to maintain a fixed number of scan lines per page during facsimile transmission. More particularly, in the preferred embodiment of the present invention the remote unit (113) maintains a fixed number of lines per page by deleting scan lines comprising a predetermined set of characters from the actual facsimile transmitted, until the number of scan lines deleted from the facsimile is equal to the number of blank scan lines generated by the remote unit (113).

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Abstract: A system and method are provided for achieving slot synchronization in a Wideband CDMA system in the presence of large initial frequency errors. A FSC matched filter having a reduced coherence window is provided for reducing degradation of a symbol due to carrier phase rotation resulting from oscillator error, thereby preventing severe loss of signal energy at the peaks of the FSC matched filter output. Additionally, a circular sliding integrator is provided to combine the accumulated disbursed signal energies due to the oscillator error and multipath interference, thereby allowing easier identification of the time index representing the time slot boundary. Further, a sorter is provided for determining a predetermined number of time index candidates representing the time slot boundary, thereby increasing the possibility that the true time index boundary is sent to the second stage of synchronization.

Abstract: A system includes a unique word correlator module which correlates a unique word field in a burst of a time division multiple access (TDMA) signal against a predefined marker sequence. Automatic timing control circuitry is coupled to the unique word correlator module. The automatic timing control circuitry derives a number of errors that are allowable during correlation of the unique word field.

Abstract: A method identifies a pulse sequence having known values and a known length in a signal. According to this method, the mathematical sign of the phase difference between samples of the signal is used to estimate whether the transmitted pulse is a 1 or a 0. Undersampling, carried out to a selectable extent, produces a relatively insensitive response to adjacent channel interference. The sum of the pulses in a window which is proportional to the length of the pulse sequence and to the extent of the undersampling is determined, with the pulse sequence being regarded as being identified at the point in time at which the sum of the pulses in this search window exceeds a threshold value.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: Pointer action in an SDH transmission apparatus is performed in a temporally evenly dispersed manner. Timings of a received VC-4 clock and a transmit VC-4 clock, whose portions corresponding to overhead are inhibited in a clustered fashion, are evened out by a receiving-side PLL circuit and a transmitting-side PLL circuit, respectively, after which their phases are compared in a phase comparator to generate a justification request. In another aspect of the present invention, the phase comparison is made between VC-4 clocks whose clock inhibit timings are dispersed. In a further aspect of the present invention, a justification request arising from a frequency difference between the transmitting and receiving sides is combined with the justification contained in the received frame.

Abstract: A multimedia decoder is provided that inserts synchronization words into elementary linear pulse-code modulation (LPCM) audio bitstreams. In one embodiment, the multimedia decoder includes a pre-parser, a memory, and an audio decoder module. The pre-parser receives a multimedia bitstream and separates it into an audio substream and a video substream, and inserts a synchronization words before each data packet in the audio substream while forming it into an elementary bitstream. The memory is coupled to the pre-parser to buffer the elementary audio bitstream, and the audio decoder module is coupled to the memory to retrieve the elementary audio bitstream and convert it into a digital audio signal. The inserted synchronization word may comprise between from four to ten bytes in length. In one particular implementation, the inserted synchronization word includes the ASCII representation of the letters LSILOGIC.

Abstract: A receiving apparatus is provided for receiving a serial signal composed of a sequence of signals transmitted through a transmission medium. In the receiving apparatus, a receiving circuit receives as a received signal a serial signal, which is a sequence of signals including at least one of a synchronizing signal and an information signal, and which includes a plurality of signals being the same as each other and being apart from each other by a predetermined time interval. Then, a delaying circuit generates a delayed signal by delaying the received signal by the predetermined time interval, and a multiplying circuit generates a multiplied signal by multiplying the received signal by the delayed signal. Finally, a detecting circuit detects at least one of the synchronizing signal and the information signal, based on the multiplied signal.

Abstract: An apparatus and method for receiving a bitstream containing timing information and respective program information, the program information is processed and associated with locally generated timing information to form an output bitstream, the locally generated timing information is synchronized to the received timing information so that the timing relationships of the received program information are preserved even after the program information is processed.

Abstract: A system for generating a signal for coupling digital audio, video and data signals in compressed form via a bus. A processing means formats the digital audio, video and data signals into superpackets for transmission via the bus. Each superpacket comprises a timestamp, and a transport packet, representative of the digital audio, video and data signals. The superpackets have a fixed duration and occur at variable intervals. Devices receive the superpacket signal and may utilize the timestamps for clock synchronization. A recording and replay device processes the variable superpacket signal occurrence for recording. Reproduced timestamps are utilized to control restoration of the superpacket signal to have substantially the duration and occurrence as when formatted for bus transmission. A simplified bus couples superpackets between devices. An indicia is added to a superpacket signal to provide automatic control of device bus interfaces.

Abstract: A conversion (20, 120, 220) system for converting an analog signal (18, 118, 218) to a digital signal (54, 154, 254) in a communications system (10), the conversion system (20, 120, 220) including an oversampled analog-to-digital converter modulator (24, 124, 224) for receiving an oversampling-clock signal (29, 129, 229) and a transmitted analog signal (18, 118, 218), the oversampled analog-to-digital converter modulator (24, 124, 224) operable to sample the analog signal (18, 118, 218) and to convert the analog signal (18, 118, 218) to a first digital signal (32, 132, 232), a time adjustor (41, 141, 241) coupled to the oversampled analog-to-digital converter modulator (24, 124, 224) for receiving the first digital signal (32, 132, 232) and a first adjustment signal (48, 148, 248), and for producing an output digital signal (54, 154, 254), and a digital signal processor unit (56, 156, 256) coupled to the time adjustor (41, 141, 241) for receiving the output digital signal (54, 154, 254) and performing timing

Abstract: A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.

Abstract: A method and apparatus for determining synchronization and loss of synchronization in a high speed multiplexed data system. The system also includes a plurality of justification control bits and a backwards compatibility flag that allows the system to operate with older systems that have fewer justification control bits.