Abstract: Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.

Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.

Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.

Abstract: A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.

Abstract: An image processing apparatus including a plurality of transfer units, a data storage, an image processing processor, and a test circuit. A plurality of captured image data are respectively assigned to the plurality of transfer units and the plurality of transfer units transfer the assigned image data. The data storage unit stores the plurality of image data which are transferred by the plurality of transfer units. The image processing processor performs image processing on the plurality of image data which are stored in the data storage unit. The test circuit tests the image processing processor in a period during which the image data are not input from the data storage unit to the image processing processor.

Abstract: An adaptive variable-length coding/decoding method performs an optimal variable-length coding and decoding depending on an intra mode/inter mode condition, quantization step size and a current zigzag scanning position, such that a plurality of variable-length coding tables having different patterns of a regular region and an escape region according to statistical characteristics of the run level data are set. One of the variable-length coding tables is selected according to mode, quantization step size and scanning position, and the orthogonal transform coefficients according to the selected variable-length coding table are variable-length-coded.

Abstract: An adaptive variable-length coding/decoding method performs an optimal variable-length coding and decoding depending on an intra mode/inter mode condition, quantization step size and a current zigzag scanning position, such that a plurality of variable-length coding tables having different patterns of a regular region and an escape region according to statistical characteristics of the run level data are set. One of the variable-length coding tables is selected according to mode, quantization step size and scanning position, and the orthogonal transform coefficients according to the selected variable-length coding table are variable-length-coded.

Abstract: An adaptive variable-length coding/decoding method performs an optimal variable-length coding and decoding depending on an intra mode/inter mode condition, quantization step size and a current zigzag scanning position, such that a plurality of variable-length coding tables having different patterns of a regular region and an escape region according to statistical characteristics of the run level data are set. One of the variable-length coding tables is selected according to mode, quantization step size and scanning position, and the orthogonal transform coefficients according to the selected variable-length coding table are variable-length-coded.

Abstract: An adaptive variable-length coding/decoding method performs an optimal variable-length coding and decoding depending on an intra mode/inter mode condition, quantization step size and a current zigzag scanning position, such that a plurality of variable-length coding tables having different patterns of a regular region and an escape region according to statistical characteristics of the run level data are set. One of the variable-length coding tables is selected according to mode, quantization step size and scanning position, and the orthogonal transform coefficients according to the selected variable-length coding table are variable-length-coded.

Abstract: A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers.